P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 65 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
9. Dynamic characteristics
[1] T
cy(clk)
= 1 / f
osc
.
[2] Calculated values are for 6-clock mode only.
Table 63. Dynamic characteristics
Over operating conditions: load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF; T
amb
=0
°
C to +70
°
C or
−
40
°
C to +85
°
C; V
DD
= 2.7 V to 3.6 V at 33 MHz; V
SS
=0V.
[1][2]
Symbol Parameter Conditions Min Typ Max Unit
f
osc
oscillator frequency X1 mode 0 - 33 MHz
X2 mode 0 - 16 MHz
IAP 0.25 - 33 MHz
t
LHLL
ALE pulse width 2T
cy(clk)
− 15 - - ns
t
AVLL
address valid to ALE LOW time T
cy(clk)
− 25 - - ns
t
LLAX
address hold after ALE LOW time T
cy(clk)
− 25 - - ns
t
LLIV
ALE LOW to valid instruction in time - - 4T
cy(clk)
− 65 ns
t
LLPL
ALE LOW to PSEN LOW time T
cy(clk)
− 25 - - ns
t
PLPH
PSEN pulse width T
cy(clk)
− 25 - - ns
t
PLIV
PSEN LOW to valid instruction in time - - 3T
cy(clk)
− 55 ns
t
PXIX
input instruction hold after PSEN time 0 - - ns
t
PXIZ
input instruction float after PSEN time - - T
cy(clk)
− 5ns
t
PXAV
PSEN to address valid time T
cy(clk)
− 8- - ns
t
AVIV
address to valid instruction in time - - 5T
cy(clk)
− 80 ns
t
PLAZ
PSEN LOW to address float time - - 10 ns
t
RLRH
RD LOW pulse width 6T
cy(clk)
− 40 - - ns
t
WLWH
WR LOW pulse width 6T
cy(clk)
− 40 - - ns
t
RLDV
RD LOW to valid data in time - - 5T
cy(clk)
− 90 ns
t
RHDX
data hold after RD time 0 - - ns
t
RHDZ
data float after RD time - - 2T
cy(clk)
− 25 ns
t
LLDV
ALE LOW to valid data in time - - 8T
cy(clk)
− 90 ns
t
AVDV
address to valid data in time - - 9T
cy(clk)
− 90 ns
t
LLWL
ALE LOW to RD or WR LOW time 3T
cy(clk)
− 25 - 3T
cy(clk)
+ 25 ns
t
AVWL
address to RD or WR LOW time 4T
cy(clk)
− 75 - - ns
t
WHQX
data hold after WR time T
cy(clk)
− 27 - - ns
t
QVWH
data output valid to WR HIGH time 7T
cy(clk)
− 70 - - ns
t
RLAZ
RD LOW to address float time - - 0 ns
t
WHLH
RD or WR HIGH to ALE HIGH time T
cy(clk)
− 25 - T
cy(clk)
+ 25 ns
