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P89LV51RD2BA,512

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P76
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 16 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
V
DD
must stay below V
bo
at least four oscillator clock periods before the brownout
detection circuit will respond.
Brownout interrupt can be enabled by setting the EBO bit (IEN1.3). If EBO bit is set and a
brownout condition occurs, a brownout interrupt will be generated to execute the program
at location 004BH. It is required that the EBO bit is cleared by software after the brownout
interrupt is serviced. Clearing EBO bit when the brownout condition is active will properly
reset the device. If brownout interrupt is not enabled, a brownout condition will reset the
program to resume execution at location 0000H. A brownout detect reset will clear the
BSEL bit (FCF.0) but will not change the SWR bit (FCF.1) and therefore will not change the
banking of the lower 8 kB of user code memory space.
6.2.5 Watchdog reset
Like a brownout detect reset, the watchdog timer reset will clear the BSEL bit (FCF.0) but
will not change the SWR bit (FCF.1) and therefore will not change the banking of the lower
8 kB of user code memory space.
The state of the SWR and BSEL bits after different types of resets is shown in Table 6.
This results in the code memory bank selections as shown.
6.2.6 Data RAM memory
The data RAM has 1024 B of internal memory. The device can also address up to 64 kB
for external data memory.
6.2.7 Expanded data RAM addressing
The P89LV51RB2/RC2/RD2 has 1 kB of RAM. See Figure 5 “Internal and external data
memory structure” on page 19.
The device has four sections of internal data memory:
1. The lower 128 B of RAM (00H to 7FH) are directly and indirectly addressable.
2. The higher 128 B of RAM (80H to FFH) are indirectly addressable.
3. The special function registers (80H to FFH) are directly addressable only.
4. The expanded RAM of 768 B (00H to 2FFH) is indirectly addressable by the move
external instruction (MOVX) and clearing the EXTRAM bit (see ‘Auxiliary function
Register’ (AUXR) in Table 4 “Special function registers” on page 11).
Table 6. Effects of reset sources on bank selection
Reset source SWR bit result
(FCF.1)
BSEL bit result
(FCF.0)
Addresses from 0000H to
1FFFH
Addresses above
1FFFH
External reset 0 0 Boot code (in block 1) User code (in block 0)
Power-on reset
Watchdog reset x 0 Retains state of SWR bit. If
SWR, BSEL = 00 then uses
boot code. If SWR,
BSEL = 10 then uses user
code.
Brownout detect reset
Software reset 1 0 User code (in block 0)
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 17 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Since the upper 128 B occupy the same addresses as the SFRs, the RAM must be
accessed indirectly. The RAM and SFRs space are physically separate even though they
have the same addresses.
When instructions access addresses in the upper 128 B (above 7FH), the MCU
determines whether to access the SFRs or RAM by the type of instruction given. If it is
indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the examples
below.
Indirect access:
MOV@R0, #data; R0 contains 90H
Register R0 points to 90H which is located in the upper address range. Data in ‘#data’ is
written to RAM location 90H rather than port 1.
Direct access:
MOV90H, #data; write data to P1
Data in ‘#data’ is written to port 1. Instructions that write directly to the address, write to
the SFRs.
To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions
must be used. The extra 768 B of memory is physically located on the chip and logically
occupies the first 768 B of external memory (addresses 000H to 2FFH).
When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX
instruction in combination with any of the registers R0, R1 of the selected bank or DPTR.
Accessing the expanded RAM does not affect ports P0, P3.6 (WR), P3.7 (RD), or P2.
With EXTRAM = 0, the expanded RAM can be accessed as in the following example.
Expanded RAM access (indirect addressing only):
MOVX@DPTR, A DPTR contains 0A0H
Table 7. AUXR - Auxiliary register (address 8EH) bit allocation
Not bit addressable; reset value 00H.
Bit 7 6 5 4 3 2 1 0
Symbol - - - - - - EXTRAM AO
Table 8. AUXR - Auxiliary register (address 8EH) bit descriptions
Bit Symbol Description
7 to 2 - Reserved for future use. Should be set to ‘0’ by user programs.
1 EXTRAM Internal/External RAM access using MOVX
@Ri/@DPTR.
When ‘0’, core attempts to access internal XRAM with address
specified in MOVX instruction. If address supplied with this instruction
exceeds on-chip available XRAM, off-chip XRAM is going to be
selected and accessed.
When ‘1’, every MOVX
@Ri/@DPTR instruction targets external data
memory by default.
0 AO ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of
1
⁄
2
the oscillator frequency. In case of AO = 1, ALE is
active only during a MOVX or MOVC.
P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 18 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
DPTR points to 0A0H and data in ‘A’ is written to address 0A0H of the expanded RAM
rather than external memory. Access to external memory higher than 2FFH using the
MOVX instruction will access external memory (0300H to FFFFH) and will perform in the
same way as the standard 8051, with P0 and P2 as data/address bus, and P3.6 and P3.7
as write and read timing signals.
When EXTRAM = 1, MOVX@Ri and MOVX@DPTR will be similar to the standard 8051.
Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output
port pins can be used to output higher order address bits. This provides external paging
capabilities. Using MOVX@DPTR generates a 16-bit address. This allows external
addressing up to 64 kB. Port 2 provides the high-order eight address bits (DPH), and
Port 0 multiplexes the low-order eight address bits (DPL) with data. Both MOVX@Ri and
MOVX@DPTR generates the necessary read and write signals (P3.6, - WR and P3.7, -
RD) for external memory use. Table 9 shows external data memory RD, WR operation
with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the 256 B of internal RAM (lower
128 B and upper 128 B). The stack pointer may not be located in any part of the expanded
RAM.
[1] Access limited to Expanded RAM address within 0 to 0FFH; cannot access 100H to 02FFH.
Table 9. External data memory RD, WR with EXTRAM bit
[1]
Register AUXR MOVX @DPTR, A or MOVX A, @DPTR MOVX @Ri, A or
MOVX A, @Ri
ADDR < 0300H ADDR ≥ 0300H ADDR = any
EXTRAM = 0
RD/WR not asserted RD/WR asserted RD/WR not asserted
EXTRAM = 1
RD/WR asserted RD/WR asserted RD/WR asserted
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P76

P89LV51RD2BA,512

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Buy P89LV51RD2BA,512
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 44PLCC
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