P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 43 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
and slave SPI devices. The SPICLK pin is the clock output and input for the master and
slave modes, respectively. The SPI clock generator will start following a write to the
master devices SPI data register. The written data is then shifted out of the MOSI pin on
the master device into the MOSI pin of the slave device. Following a complete
transmission of one byte of data, the SPI clock generator is stopped and the SPIF flag is
set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) and
the Serial Port Interrupt Enable bit (ES) are both set.
An external master drives the Slave Select input pin, SS/P1[4], low to select the SPI
module as a slave. If SS/P1[4] has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock. Figure 17 and Figure 18
show the four possible combinations of these two bits.
Fig 16. SPI master-slave interconnection
002aaa528
8-BIT SHIFT REGISTER
MSB master LSB
SPI
CLOCK GENERATOR
MISO MISO
MOSI MOSI
SPICLK SPICLK
SS SS
8-BIT SHIFT REGISTER
MSB slave LSB
V
SS
V
DD
Table 28. SPCTL - SPI control register (address D5H) bit allocation
Bit addressable; reset source(s): any reset; reset value: 0000 0000B.
Bit 7 6 5 4 3 2 1 0
Symbol SPIE SPEN DORD MSTR CPOL CPHA PSC1 PSC0
Table 29. SPCTL - SPI control register (address D5H) bit descriptions
Bit Symbol Description
7 SPIE If both SPIE and ES are set to one, SPI interrupts are enabled.
6 SPEN SPI enable bit. When set enables SPI.
5 DORD Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
4 MSTR Master/slave select. 1 = master mode, 0 = slave mode.
3 CPOL Clock polarity. 1 = SPICLK is high when idle (active LOW), 0 = SPICLK
is low when idle (active HIGH).
