P89LV51RB2_RC2_RD2_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 28 of 76
NXP Semiconductors
P89LV51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Table 15. TMOD - Timer/counter mode control register (address 89H) bit descriptions
Bit Symbol Description
T1/T0 Bits controlling Timer1/Timer0
GATE Gating control when set. Timer/counter ‘x’ is enabled only while ‘INTx’
INTx pin is HIGH and ‘TRx’ control pin is set. When cleared, Timer ‘x’
is enabled whenever ‘TRx’ control bit is set.
C/
T Gating Timer or Counter Selector cleared for Timer operation (input
from internal system clock). Set for Counter operation (input from ‘Tx’
input pin).
Table 16. TMOD - Timer/counter mode control register (address 89H) M1/M0 operating
mode
M1 M0 Operating mode
0 0 0 8048 timer ‘TLx’ serves as 5-bit prescaler
0 1 1 16-bit Timer/counter ‘THx’ and ‘TLx' are cascaded; there
is no prescaler.
1 0 2 8-bit auto-reload Timer/counter ‘THx’ holds a value which
is to be reloaded into ‘TLx’ each time it overflows.
1 1 3 (Timer 0) TL0 is an 8-bit Timer/counter controlled by the
standard Timer 0 control bits. TH0 is an 8-bit timer only
controlled by Timer 1 control bits.
1 1 3 (Timer 1) Timer/counter 1 stopped.
Table 17. TCON - Timer/counter control register (address 88H) bit allocation
Bit addressable; reset value: 0000 0000B; reset source(s): any reset.
Bit 7 6 5 4 3 2 1 0
Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Table 18. TCON - Timer/counter control register (address 88H) bit descriptions
Bit Symbol Description
7 TF1 Timer 1 overflow flag. Set by hardware on Timer/counter overflow.
Cleared by hardware when the processor vectors to Timer 1 Interrupt
routine, or by software.
6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/counter 1
on/off.
5 TF0 Timer 0 overflow flag. Set by hardware on Timer/counter overflow.
Cleared by hardware when the processor vectors to Timer 0 Interrupt
routine, or by software.
4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/counter 0
on/off.
3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.