AX5051-1-WD1 Datasheet AX5051-1-TW30, AX5051-1-TA05, AX5051-1-WD1 | P13-P15

AX5051

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CIRCUIT DESCRIPTION

The AX5051 is a true single chip low−power CMOS

transceiver primarily for use in SRD bands. The on−chip

transceiver consists of a fully integrated RF front−end with

modulator, and demodulator. Base band data processing is

implemented in an advanced and flexible communication

controller that enables user−friendly communication via the

SPI interface.

AX5051 can be operated from 2.2 V to 3.6 V power

supply over a temperature range from −40°C to 85°C, it

consumes 11 − 45 mA for transmitting depending on the

output power, 19 mA for receiving in high sensitivity mode

and 18 mA for receiving in low power mode.

The AX5051 features make it an ideal interface for

integration into various battery powered SRD solutions such

as ticketing or as transceiver for telemetric applications e.g.

in sensors. As primary application, the transceiver is

intended for UHF radio equipment in accordance with the

European Telecommunication Standard Institute (ETSI)

specification EN 300 220−1 and the US Federal

Communications Commission (FCC) standard CFR47, part

15. The use of AX5051 in accordance to FCC Par 15.247,

allows for improved range in the 915 MHz band.

Additionally AX5051 is compatible with the low frequency

standards of 802.15.4 (ZigBee). It therefore incorporates a

DSSS engine, which spreads data on the transmitter and

despreads data for the receiver. Spreading and despreading

is possible on all data rates and modulation schemes. The net

transfer rate is reduced by a factor of 15 in this case. For

802.15.4 either 600 or 300 kbps modes have to be chosen.

The AX5051 sends and receives data via the SPI port in

frames. This standard operation mode is called Frame Mode.

Pre and post ambles as well as checksums can be generated

automatically. Interrupts control the data flow between a

controller and the AX5051.

The AX5051 behaves as a SPI slave interface.

Configuration of the AX5051 is also done via the SPI

interface.

AX5051 supports any data rate from 1 kbps to 350 kbps

for FSK and MSK and from 1 kbps for 600 kbps for ASK and

10 kbps to 600 kbps PSK. To achieve optimum performance

for specific data rates and modulation schemes several

are outlined in the following, for details see the AX5051

Programming Manual.

The receiver supports multi−channel operation for all data

rates and modulation schemes.

Voltage Regulator

The AX5051 uses an on−chip voltage regulator to create

a stable supply voltage for the internal circuitry at pin VREG

from the primary supply VDD_IO. All VDD pins of the

device must be connected to VREG. The antenna pins

ANTP and ANTN must be DC biased to VREG. The I/O

level of the digital pins is VDD_IO.

The voltage regulator requires a 1 mF low ESR capacitor

at pin VREG.

In power−down mode the voltage regulator typically

outputs 1.7 V at VREG, if it is powered−up its output rises

to typically 2.5 V. At device power−up the regulator is in

power−down mode.

The voltage regulator must be powered−up before receive

or transmit operations can be initiated. This is handled

automatically when programming the device modes via the

PWRMODE register.

check if the regulated voltage is above 1.3 V or 2.3 V, sticky

versions of the bits are provided that can be used to detect

low power events (brown−out detection).

Crystal Oscillator

The on−chip crystal oscillator allows the use of an

inexpensive quartz crystal as the RF generation subsystem’s

timing reference. Although a wider range of crystal

frequencies can be handled by the crystal oscillator circuit,

it is recommended to use 16 MHz as reference frequency for

ASK and PSK modulations independent of the data rate. For

FSK it is recommended to use a 16 MHz crystal for data rates

below 200 kbps and 24 MHz for data rates above 200 kbps.

The oscillator circuit is enabled by programming the

PWRMODE register. At power−up it is not enabled.

To adjust the circuit’s characteristics to the quartz crystal

being used without using additional external components,

both the transconductance and the tuning capacitance of the

crystal oscillator can be programmed.

The transconductance is programmed via register bits

XTALOSCGM[3:0] in register XTALOSC.

The integrated programmable tuning capacitor bank

makes it possible to connect the oscillator directly to pins

CLK16N and CLK16P without the need for external

capacitors. It is programmed using bits XTALCAP[5:0] in

To synchronize the receiver frequency to a carrier signal,

the oscillator frequency could be tuned using the capacitor

bank however, the recommended method to implement

frequency synchronization is to make use of the high

resolution RF frequency generation sub−system together

with the Automatic Frequency Control, both are described

further down.

Alternatively a single ended reference (TXCO, CXO)

may be used. The CMOS levels should be applied to

CLK16P via an AC coupling with the crystal oscillator

enabled.

SYSCLK Output

The SYSCLK pin outputs the reference clock signal

divided by a programmable integer. Divisions from 1 to

2048 are possible. For divider ratios > 1 the duty cycle is

AX5051

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50%. Bits SYSCLK[3:0] in the PINCFG1 register set the

divider ratio. The SYSCLK output can be disabled.

Outputting a frequency that is identical to the IF frequency

(default 1 MHz) on the SYSCLK pin is not recommended

during receive operation, since it requires extensive

decoupling on the PCB to avoid interference.

Power−on−reset (POR) and RESET_N Input

AX5051 has an integrated power−on−reset block. No

external POR circuit or signal at the RESET_N pin is

required, prior to POR the RESET_N pin is disabled.

After POR the AX5051 can be reset in two ways:

1. By SPI accesses: the bit RST in the PWRMODE

2. Via the RESET_N pin: A low pulse is applied at

the RESET_N pin. With the rising edge of

RESET_N the device goes into its operational

state.

After POR or reset all registers are set to their default

values.

If the RESET_N pin is not used it must be tied to

VDD_IO.

RF Frequency Generation Subsystem

The RF frequency generation subsystem consists of a

fully integrated synthesizer, which multiplies the reference

frequency from the crystal oscillator to get the desired RF

frequency. The advanced architecture of the synthesizer

enables frequency resolutions of 1 Hz, as well as fast settling

times of 5 – 50 ms depending on the settings (see section:

AC Characteristics). Fast settling times mean fast start−up

and fast RX/TX switching, which enables low−power

system design.

For receive operation the RF frequency is fed to the mixer,

for transmit operation to the power−amplifier.

The frequency must be programmed to the desired carrier

frequency. The RF frequency shift by the IF frequency that

is required for RX operation, is automatically set when the

receiver is activated and does not need to be programmed by

the user. The default IF frequency is 1 MHz. It can be

programmed to other values. Changing the IF−frequency

and thus the center frequency of the digital channel filter can

be used to adapt the blocking performance of the device to

specific system requirements.

The synthesizer loop bandwidth can be programmed. This

serves three purposes:

1. Start−up time optimization, start−up is faster for

higher synthesizer loop bandwidths.

2. TX spectrum optimization, phase−noise at

300 kHz to 1 MHz distance from the carrier

improves with lower synthesizer loop bandwidths.

3. Adaptation of the bandwidth to the data−rate. For

transmission of FSK and MSK it is required that

the synthesizer bandwidth must be in the order of

the data−rate.

VCO

An on−chip VCO converts the control voltage generated

by the charge pump and loop filter into an output frequency.

This frequency is used for transmit as well as for receive

operation. The frequency can be programmed in 1 Hz steps

in the FREQ registers. For operation in the 433 MHz band,

the BANDSEL bit in the PLLLOOP register must be

programmed.

VCO Auto−Ranging

The AX5051 has an integrated auto−ranging function,

which allows to set the correct VCO range for specific

frequency generation subsystem settings automatically.

Typically it has to be executed after power−up. The function

is initiated by setting the RNG_START bit in the

PLLRANGING register. The bit is readable and a 0 indicates

the end of the ranging process. The RNGERR bit indicates

the correct execution of the auto−ranging.

Loop Filter and Charge Pump

The AX5051 internal loop filter configuration together

with the charge pump current sets the synthesizer loop band

width. The loop−filter has three configurations that can be

programmed via the register bits FLT[1:0] in register

PLLLOOP, the charge pump current can be programmed

using register bits PLLCPI[1:0] also in register PLLLOOP.

Synthesizer bandwidths are typically 50 – 500 kHz

depending on the PLLLOOP settings, for details see the

section: AC Characteristics.

Registers

Table 12. REGISTERS

PLLLOOP

FLT[1:0] Synthesizer loop filter bandwidth, recommended usage is to increase the bandwidth for faster

settling time, bandwidth increases of factor 2 and 5 are possible.

PLLCPI[2:0] Synthesizer charge pump current, recommended usage is to decrease the bandwidth (and

improve the phase−noise) for low data−rate transmissions.

BANDSEL Switches between 868 MHz / 915 MHz and 433 MHz bands

FREQ Programming of the carrier frequency

IFFREQHI, IFFREQLO Programming of the IF frequency

PLLRANGING Initiate VCO auto−ranging and check results

AX5051

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RF Input and Output Stage (ANTP/ANTN)

The AX5051 uses fully differential antenna pins. RX/TX

switching is handled internally; an external RX/TX switch

is not required.

LNA

The LNA amplifies the differential RF signal from the

antenna and buffers it to drive the I/Q mixer. An external

matching network is used to adapt the antenna impedance to

the IC impedance. A DC feed to the regulated supply voltage

VREG must be provided at the antenna pins. For

recommendations see section: Application Information.

I/Q Mixer

The RF signal from the LNA is mixed down to an IF of

typically 1 MHz. I− and Q−IF signals are buffered for the

analog IF filter.

In TX mode the PA drives the signal generated by the

frequency generation subsystem out to the differential

antenna terminals. The output power of the PA is

programmed via bits TXRNG[3:0] in the register TXPWR.

Output power as well as harmonic content will depend on the

external impedance seen by the PA, recommendations are

given in the section: Application Information.

Analog IF Filter

The mixer is followed by a complex band−pass IF filter,

which suppresses the down−mixed image while the wanted

signal is amplified. The center frequency of the filter is

1 MHz, with a pass−band width of 1 MHz. The RF

frequency generation subsystem must be programmed in

such a way that for all possible modulation schemes the IF

frequency spectrum fits into the pass−band of the analog

filter.

Digital IF Channel Filter and Demodulator

The digital IF channel filter and the demodulator extract

the data bit−stream from the incoming IF signal. They must

be programmed to match the modulation scheme as well as

the data rate. Inaccurate programming will lead to loss of

sensitivity.

The channel filter offers bandwidths of 40 kHz up to

600 kHz.

For detailed instructions how to program the digital

channel filter and the demodulator see the AX5051

Programming Manual, an overview of the registers involved

is given in the following table. The register setups typically

must be done once at power−up of the device.

Table 13. REGISTERS

CICDEC This register programs the bandwidth of the digital channel filter.

DATARATEHI, DATARATELO These registers specify the receiver bit rate, relative to the channel filter bandwidth.

TMGGAINHI, TMGGAINLO These registers specify the aggressiveness of the receiver bit timing recovery. More aggressive

settings allow the receiver to synchronize with shorter preambles, at the expense of more timing

jitter and thus a higher bit error rate at a given signal−to−noise ratio.

MODULATION This register selects the modulation to be used by the transmitter and the receiver, i.e. whether

ASK, PSK , FSK, MSK or OQPSK should be used.

PHASEGAIN, FREQGAIN,

FREQGAIN2, AMPLGAIN

These registers control the bandwidth of the phase, frequency offset and amplitude tracking loops.

Recommended settings are provided in the Programming Manual.

AGCATTACK, AGCDECAY These registers control the AGC (automatic gain control) loop slopes, and thus the speed of gain

adjustments. The faster the bit rate, the faster the AGC loop should be. Recommended settings

are provided in the Programming Manual.

TXRATE These registers control the bit rate of the transmitter.

FSKDEV These registers control the frequency deviation of the transmitter in FSK mode. The receiver does

not explicitly need to know the frequency deviation, only the channel filter bandwidth has to be set

wide enough for the complete modulation to pass.

Encoder

The encoder is located between the Framing Unit, the

Demodulator and the Modulator. It can optionally transform

the bit−stream in the following ways:

• It can invert the bit stream.

• It can perform differential encoding. This means that a

zero is transmitted as no change in the level, and a one

is transmitted as a change in the level. Differential

encoding is useful for PSK, because PSK transmissions

can be received either as transmitted or inverted, due to

the uncertainty of the initial phase. Differential

encoding / decoding removes this uncertainty.

• It can perform Manchester encoding. Manchester

encoding ensures that the modulation has no DC

content and enough transitions (changes from 0 to 1 and

from 1 to 0) for the demodulator bit timing recovery to

function correctly, but does so at a doubling of the data

rate.

• It can perform Spectral Shaping. Spectral Shaping

removes DC content of the bit stream, ensures

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AX5051-1-WD1

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IC RF TXRX ISM<1GHZ 28VFQFN

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