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AX5051-1-WD1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
AX5051
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22
Table 21. CONTROL REGISTER MAP
Addr Description
Bit
ResetDirNameAddr Description
01234567
ResetDirName
47 AMPLGAIN RW –––00110 – – – reserved AMPLGAIN(3:0) Amplitude Gain
48 TRKAMPLHI R –––––––– TRKAMPL(15:8) Amplitude Tracking
49 TRKAMPLLO R –––––––– TRKAMPL(7:0) Amplitude Tracking
4A TRKPHASEHI R –––––––– – – – – TRKPHASE(11:8) Phase Tracking
4B TRKPHASELO R –––––––– TRKPHASE(7:0) Phase Tracking
4C TRKFREQHI R –––––––– TRKFREQ(15:8) Frequency
Tracking
4D TRKFREQLO R –––––––– TRKFREQ(7:0) Frequency
Tracking
Crystal Oscillator, Part 2
4F
XTALCAP RW −−000000 − − XTALCAP(5:0) Crystal oscillator
tuning capacitance
Misc
72
PLLVCOI RW −−000100 − − reserved VCO_I[2:0] Synthesizer VCO
current
Must be set to 001
7A LOCURST RW 00110000 LOCUR
ST
reserved LOCURST
Must be set to 1
7C rEF RW −−100011 − − reserved REF_I[2:0] Reference adjust
7D RXMISC RW −−110110 − − reserved RXIMIX(1:0) Misc RF settings
RXIMIX(1:0) must
be set to 01
AX5051
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23
APPLICATION INFORMATION
Typical Application Diagram
Figure 4. Typical Application Diagram
TST1
RESET_N
NC
GND
ANTP
ANTN
GND
VDD
CLK
MISO
IRQ
VDD_IO
NC
VREG
GND
GND
ANTENNA
TO/FROM MICRO −CONTROLLER
From Power
Supply
N2
GND
SYSCLK
SEL
VDD
MOSI
1 mF
AX5051
CLK16N
CLK16P
NC
NC
VREG
NC
GND
It is mandatory to add 1 mF (low ESR) between VREG and
GND.
Decoupling capacitors are not all drawn. It is
recommended to add 100 nF decoupling capacitor for every
VDD and VDD_IO pin. In order to reduce noise on the
antenna inputs it is recommended to add 27 pF on the VDD
pins close to the antenna interface.
AX5051
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24
Antenna Interface Circuitry
The ANTP and ANTN pins provide RF input to the LNA
when AX5051 is in receiving mode, and RF output from the
PA when AX5051 is in transmitting mode. A small antenna
can be connected with an optional translation network. The
network must provide DC power to the PA and LNA. A
biasing to VREG is necessary.
Beside biasing and impedance matching, the proposed
networks also provide low pass filtering to limit spurious
emission.
Single−ended Antenna Interface
Figure 5. Structure of the Antenna Interface to 50 W Single−ended Equipment or Antenna
CC1
CB1
LT2
IC Antenna
Pins
VRE
G
VREG
LT1
LC2
LC1
CM1
LB1
CB2
LB2
CF1
CF2
LF1
CT1
CT2
CC2
CM2
50 W single−ended
equipment or
antenna
Optional filter stage
to suppress TX
harmonics
Table 22.
Frequency Band
LC1,2
[nH]
CC1,2
[pF]
LT1,2
[nH]
CT1,2
[pF]
CM1,2
[pF]
LB1,2
[nH]
CB1,2
[pF]
LF1
[nH]
CF1,2
[pF]
868 / 915 MHz 68 0.9 12 18 2.4 12 2.7
0 W
NC
433 MHz 120 2.2 39 7.5 6.0 27 5.2
0 W
NC
Voltage Regulator
The AX5051 has an integrated voltage regulator, which
generates a stable supply voltage VREG from the voltage
applied at VDD_IO. Use VREG to supply all the VDD
supply pins.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

AX5051-1-WD1

Mfr. #:
Buy AX5051-1-WD1
Manufacturer:
ON Semiconductor
Description:
IC RF TXRX ISM<1GHZ 28VFQFN
Lifecycle:
New from this manufacturer.
Delivery:
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