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9DB823BFLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
ICS9DB823B
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2 AND QPI
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2 AND QPI 16
ICS9DB823B REV F 091812
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated
(depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the
PD# drive mode bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the
PD# drive mode bit is set to ‘1’, both DIF and DIF# are tri-stated.
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is
set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
ICS9DB823B
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2 AND QPI
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2 AND QPI 17
ICS9DB823B REV F 091812
DIF_STOP#
The DIF_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The DIF_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
DIF_STOP# - Assertion
Asserting DIF_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the DIF_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When
the DIF_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
DIF_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs
is 2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the DIF_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
DIF_STOP_1 (Stop_Mode = Driven, PD_Mode = Driven)
DIF_STOP_2 (Stop_Mode = Tristate, PD_Mode = Driven)
ICS9DB823B
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2 AND QPI
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1, GEN2 AND QPI 18
ICS9DB823B REV F 091812
DIF_STOP_3 (Stop_Mode = Driven, PD_Mode = Tristate)
DIF_STOP_4 (Stop_Mode = Tristate, PD_Mode = Tristate)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

9DB823BFLFT

Mfr. #:
Buy 9DB823BFLFT
Manufacturer:
IDT
Description:
Clock Buffer 8 OUTPUT PCIE GEN2 BUFFER w/QPI
Lifecycle:
New from this manufacturer.
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