MC100EL17DWG Datasheet MC100EL17DWG, SC68C2550BIB48,128, SC68C2550BIB48,151 | P10-P12

Product data sheet Rev. 03 — 9 October 2009 10 of 36

NXP Semiconductors

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.6 DMA operation

The SC68C2550B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an

empty location(s). The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA

mode is de-activated (DMA Mode 0), the SC68C2550B activates the interrupt output pin

for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1),

the user takes the advantage of block mode operation by loading or unloading the FIFO in

a block sequence determined by the receive trigger level and the transmit FIFO. In this

mode, the SC68C2550B sets the TXRDYn (or RXRDYn) output pin when characters in the

transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive

trigger level.

Fig 3. Crystal oscillator connection

Table 6. Baud rate generator programming table using a 1.8432 MHz clock

Output

baud rate

Output

16× clock divisor

(decimal)

Output

16× clock divisor

(HEX)

DLM

program value

(HEX)

DLL

program value

(HEX)

50 2304 900 09 00

75 1536 600 06 00

110 1047 417 04 17

150 768 300 03 00

300 384 180 01 80

600 192 C0 00 C0

1200 96 60 00 60

2400 48 30 00 30

3600 32 20 00 20

4800 24 18 00 18

7200 16 10 00 10

9600 12 0C 00 0C

19.2 k 6 06 00 06

38.4 k 3 03 00 03

57.6 k 2 02 00 02

115.2 k 1 01 00 01

002aab325

33 pF

XTAL1 XTAL2

1.8432 MHz

22 pF

Product data sheet Rev. 03 — 9 October 2009 11 of 36

NXP Semiconductors

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.7 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally

(see Figure 4). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the Loopback mode, the transmitter output pin (TXn) and the receiver input pin (RXn)

are disconnected from their associated interface pins, and instead are connected together

internally. The CTSn, DSRn, CDn, and RIn pins are disconnected from their normal

modem control inputs pins, and instead are connected internally to MCR[1] RTS, MCR[0]

DTR, MCR[3] (OP2) and MCR[2] (OP1). Loopback test data is entered into the transmit

holding register via the user data bus interface, D0 to D7. The transmit UART serializes

the data and passes the serial data to the receive UART via the internal loopback

connection. The receive UART converts the serial data back into parallel data that is then

made available at the user data interface D0 to D7. The user optionally compares the

received data to the initial transmitted data for verifying error-free operation of the UART

transmit/receive circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational.

Product data sheet Rev. 03 — 9 October 2009 12 of 36

NXP Semiconductors

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Fig 4. Internal Loopback mode diagram

CTSA, CTSB

TRANSMIT

FIFO

REGISTERS

TXA, TXB

RECEIVE

SHIFT

RECEIVE

FIFO

REGISTERS

RXA, RXB

INTERCONNECT BUS LINES

AND

CONTROL SIGNALS

SC68C2550B

TRANSMIT

SHIFT

XTAL2XTAL1

002aab336

DATA BUS

AND

CONTROL

LOGIC

SELECT

LOGIC

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

MODEM

CONTROL

LOGIC

RTSA, RTSB

DSRA, DSRB

DTRA, DTRB

RIA, RIB

(OP1A, OP1B)

CDA, CDB

(OP2A, OP2B)

MCR[4] = 1

D0 to D7

R/W

RESET

A0 to A3

IRQ

TXRDYA, TXRDYB

RXRDYA, RXRDYB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

MC100EL17DWG

Mfr. #:

Buy MC100EL17DWG

Manufacturer:

ON Semiconductor

Description:

Buffers & Line Drivers 5V ECL Quad Diff

Lifecycle:

New from this manufacturer.

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MC100EL17DWG

MC100EL17DWG

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