SC68C2550B_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 9 October 2009 16 of 36
NXP Semiconductors
SC68C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
programmed trigger level. However, the FIFO continues to fill regardless of the
programmed level until the FIFO is full. RXRDYn pin packages transitions LOW when the
FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.
7.3.2 FIFO mode
Table 9. FIFO Control Register bits description
Bit Symbol Description
7:6 FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive FIFO
interrupt.
logic 0 (or cleared) = normal default condition
logic 1 = receive trigger level
An interrupt is generated when the number of characters in the FIFO equals the
programmed trigger level. However, the FIFO will continue to be loaded until it
is full. Refer to
Table 10.
5:4 FCR[5:4] not used; initialized to logic 0
3 FCR[3] DMA mode select
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC68C2550B is in the 68C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled;
FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the
transmit FIFO or transmit holding register, the
TXRDYn pin will be a logic 0.
Once active, the
TXRDYn pin will go to a logic 1 after the first character is
loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC68C2550B is in mode ‘0’
(FCR[0] = logic 0), or in the FIFO mode (FCR[3] = logic 0) and there is at least
one character in the receive FIFO, the
RXRDYn pin will be a logic 0. Once
active, the
RXRDYn pin will go to a logic 1 when there are no more characters
in the receiver.
Transmit operation in mode ‘1’: When the SC68C2550B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a logic 1 when the
transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations
are empty.
Receive operation in mode ‘1’: When the SC68C2550B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a
Receive Time-Out has occurred, the
RXRDYn pin will go to a logic 0. Once
activated, it will go to a logic 1 after there are no more characters in the FIFO.
2 FCR[2] XMIT FIFO reset
logic 0 = transmit FIFO not reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after clearing the FIFO.
1 FCR[1] RCVR FIFO reset
logic 0 = receive FIFO not reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO counter
logic (the receive shift register is not cleared or altered). This bit will return to
a logic 0 after clearing the FIFO.
