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MC100EL17DWG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
SC68C2550B_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 9 October 2009 22 of 36
NXP Semiconductors
SC68C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.9 Scratchpad Register (SPR)
The SC68C2550B provides a temporary data register to store 8 bits of user information.
7.10 SC68C2550B external reset condition
8. Limiting values
Table 20. Reset state for registers
Register Reset state
IER IER[7:0] = 0
FCR FCR[7:0] = 0
ISR ISR[7:1] = 0; ISR[0] = 1
LCR LCR[7:0] = 0
MCR MCR[7:0] = 0
LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR MSR[7:4] = input signals; MSR[3:0] = 0
SPR SFR[7:0] = 1
DLL DLL[7:0] = X
DLM DLM[7:0] = X
Table 21. Reset state for outputs
Output Reset state
TXA, TXB logic 1
OP2A, OP2B logic 1
RTSA, RTSB logic 1
DTRA, DTRB logic 1
IRQ 3-state condition
Table 22. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage - 7 V
V
n
voltage on any other pin at D7 to D0 GND − 0.3 V
CC
+ 0.3 V
at any input only pin GND − 0.3 5.3 V
T
amb
ambient temperature operating −40 +85 °C
T
stg
storage temperature −65 +150 °C
P
tot
/pack total power dissipation
per package
- 500 mW
SC68C2550B_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 9 October 2009 23 of 36
NXP Semiconductors
SC68C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
9. Static characteristics
[1] Except XTAL2, V
OL
= 1 V typical.
Table 23. Static characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
±
10 %, unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
V
IL(clk)
clock LOW-level input voltage −0.3 0.45 −0.3 0.6 −0.5 0.6 V
V
IH(clk)
clock HIGH-level input voltage 1.8 V
CC
2.4 V
CC
3.0 V
CC
V
V
IL
LOW-level input voltage except X1 clock −0.3 0.65 −0.3 0.8 −0.5 0.8 V
V
IH
HIGH-level input voltage except X1 clock 1.6 - 2.0 - 2.2 - V
V
OL
LOW-level output voltage on all outputs
[1]
I
OL
=5mA
(data bus)
-----0.4V
I
OL
=4mA
(other outputs)
---0.4--V
I
OL
=2mA
(data bus)
- 0.4 - - - - V
I
OL
= 1.6 mA
(other outputs)
- 0.4 - - - - V
V
OH
HIGH-level output voltage I
OH
= −5mA
(data bus)
----2.4-V
I
OH
= −1mA
(other outputs)
--2.0---V
I
OH
= −800 µA
(data bus)
1.85 - - - - - V
I
OH
= −400 µA
(other outputs)
1.85 - - - - - V
I
LIL
LOW-level input leakage
current
- ±10 - ±10 - ±10 µA
I
L(clk)
clock leakage current - ±30 - ±30 - ±30 µA
I
CC
supply current f = 5 MHz - 3.5 - 4.5 - 4.5 mA
C
i
input capacitance - 5-5-5pF
SC68C2550B_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 9 October 2009 24 of 36
NXP Semiconductors
SC68C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
10. Dynamic characteristics
[1] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
[2] Applies to external clock; crystal oscillator maximum = 24 MHz.
[3]
[4] Reset pulse must happen when CS is inactive.
Table 24. Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
±
10 %, unless specified otherwise.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V and 5 V Unit
Min Max Min Max
t
d1
R/W to chip select 10 - 10 - ns
t
d2
read cycle delay 25 pF load 20 - 20 - ns
t
d3
delay from CS to data 25 pF load - 77 - 26 ns
t
d4
data disable time 25 pF load - 15 - 15 ns
t
d6
write cycle delay 25 - 25 - ns
t
d7
delay from write to output 25 pF load - 100 - 33 ns
t
d8
delay to set interrupt from modem
input
25 pF load - 100 - 24 ns
t
d9
delay to reset interrupt from read 25 pF load - 100 - 24 ns
t
d10
delay from stop to set interrupt - 1T
RCLK
[1]
-1T
RCLK
[1]
ns
t
d11
delay from read to reset interrupt 25 pF load - 100 - 29 ns
t
d12
delay from start to set interrupt - 100 - 100 ns
t
d13
delay from write to transmit start 8T
RCLK
[1]
24T
RCLK
[1]
8T
RCLK
[1]
24T
RCLK
[1]
ns
t
d14
delay from write to reset interrupt - 100 - 70 ns
t
d15
delay from stop to set RXRDY-1T
RCLK
[1]
-1T
RCLK
[1]
ns
t
d16
delay from read to reset RXRDY - 100 - 75 ns
t
d17
delay from write to set TXRDY - 100 - 70 ns
t
d18
delay from start to reset TXRDY - 16T
RCLK
[1]
- 16T
RCLK
[1]
ns
t
h2
R/W hold time from CS 10 - 10 - ns
t
h3
data hold time 15 - 15 - ns
t
h4
address hold time 15 - 15 - ns
t
WH
pulse width HIGH 10 - 6 - ns
t
WL
pulse width LOW 10 - 6 - ns
f
XTAL
clock speed
[2][3]
- 48 - 80 MHz
t
(RESET)
RESET pulse width
[4]
200 - 200 - ns
t
su1
address set-up time 10 - 10 - ns
t
su2
data set-up time 16 - 16 - ns
t
w(CS)
CS pulse width 77 - 30 - ns
f
XTAL
1
t
wclk()
---------------
=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

MC100EL17DWG

Mfr. #:
Buy MC100EL17DWG
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 5V ECL Quad Diff
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New from this manufacturer.
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