155Mbps to 2.5Gbps Burst-Mode Laser Driver
10 Maxim Integrated
MAX3643
Detailed Description
The MAX3643 laser driver includes a bias current gen-
erator, bias current monitor, modulation current genera-
tor, laser drive outputs, and monitor diode sample and
hold. LVPECL-compatible inputs are provided for both
high-speed data and burst enable. The high-speed
burst-enable input signal is replicated on an LVCMOS
output for use by the controller.
Laser Diode Modulation and
Bias Current Generators
Laser diode modulation current amplitude is controlled
by the current out of the MODSET pin, and bias current
by the current out of the BIASSET pin, according to:
I
MOD
= I
MODSET
x 88
I
BIAS
= I
BIASSET
x 88
A voltage source and two op amps are provided to
enable I
MODSET
and I
BIASSET
to be set using either a
resistor to ground or a current digital-to-analog convert-
er (DAC). The high-impedance op amp reference input
can be externally controlled, so that the modulation and
bias currents can also be set using voltage DACs.
Laser Diode Modulation and
Bias Current Limiter
Typical laser diodes have an absolute maximum rating
of 150mA. To reduce the possibility of laser damage,
the modulation current and bias current are shut off if
the sum I
MOD
+ I
BIAS
attempts to exceed the limit set
by R
IMAX
; see the
Typical Operating Characteristics
.
Bias Current Monitor
The laser diode bias current can be monitored by measur-
ing the voltage across an external load resistor connected
from BCMON to ground. For example, a 1kΩ resistor from
BCMON to ground gives the following relationship:
The voltage at BCMON must be below 1.4V for proper
operation.
Output Drivers
The modulation current ranges from 10mA to 85mA, as
set by the current through MODSET. The laser modula-
tion current output OUT+ is optimized to drive a 15Ω
load, and must be DC-coupled. A series damping resis-
tor, R
D
, provides impedance matching to the laser
diode. The combined value of the series damping resis-
tor and the laser diode equivalent series resistance
should be close to 15Ω. An RC shunt compensation
network, R
COMP
/C
COMP
, connected between the laser
diode cathode and ground should also be provided to
reduce optical output aberrations and duty-cycle dis-
tortion caused by laser diode parasitic inductance. The
values of R
COMP
and C
COMP
can be adjusted to match
the laser diode and PCB layout characteristics for opti-
mal optical eye performance (refer to Application
Note 274:
HFAN-02.0: Interfacing Maxim Laser Drivers
with Laser Diodes
). The OUT- pin is connected through
a 15Ω resistor and switching diode to the laser diode
anode. The switching diode at OUT- improves the opti-
cal output eye and burst-enable delay by better match-
ing the laser diode characteristics.
For data rates greater than 1Gbps, a parallel RL peak-
ing network, R
P
/L
P
, connected between the laser diode
anode and V
CC
is recommended. This network creates
a differential drive for the laser diode to improve rise/fall
times and reduce jitter. The values of R
P
and L
P
are
also adjusted to match the laser diode and PCB layout
characteristics for optimal optical eye performance.
The bias current ranges from 1mA to 70mA, as set by
the current through BIASSET. Current in the BIAS out-
put switches at high speed when bursting; therefore,
the BIAS+ pin should be connected directly through a
resistor, equal to R
D
as determined above, to the laser
cathode. The BIAS- pin is connected through a 10Ω
resistor and switching diode to V
CC
.
When the BEN input is high, the laser driver sinks bias
and modulation current according to the settings at
MODSET and BIASSET. When the BEN input is low, the
BIAS+ and OUT+ currents both shut off within 2ns.
Note that when BEN is low, the bias current is shunted
through the BIAS- output and the modulation current
through the OUT- output.
Monitor Diode Sample and Hold
Laser monitor diode current is only generated when
there is an optical output (BEN is active). When BEN is
inactive, the monitor current is zero, reflecting the fact
that the laser is off. A sample-and-hold circuit, trig-
gered by the state of the BEN input, is provided in the
MAX3643. During the burst-enable active period, the
voltage present at MDIN is stored on an internal sam-
ple-and-hold capacitor; and during the burst-enable
inactive period, that voltage is output on MDOUT; see
the timing diagram in Figure 2.
While the internal sample-and-hold is sampling (BEN
active), MDOUT voltage takes a 1.2V reference level.
