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IR3521MTRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
IR3521
Page 19 V3.03
SVID OFF TRANSISTION
SVID programmed voltage
SVID
TRANSITION
STARTUP
TIME
(12V)
START
DELAY
VCC
ENABLE
1.4V
VOUT
PGOOD
3.92V
SS/DEL
4.0V
NORMAL
OPERATION
VDACx
SVID set voltage
2-Bit Boot
VID Voltage
EAOUT
SVID OFF COMMAND
SVID OFF COMMAND
PWROK
2-Bit Boot
VID On-Hold
2-Bit Boot
VID On-Hold
0.5V
SVID ON TRANSISTION
SVID ON COMMAND
SVID ON COMMAND
1.4V
VID ON
THE FLY
PROCESSION
0.8V
SVC
SVD
2-Bit Boot VID
READ & STORE
2-Bit Boot VID
READ & STORE
SVID
TRANSITION
Figure 11 SVID Start-up Sequence Transitions
IR3521
Page 20 V3.03
Serial VID Interface Protocol and VID-on-the-fly Transition
The IR3521 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which are
based on High-Speed I
2
C. SVID commands from an AMD processor are communicated through SVID bus pins
SVC and SVD. The SVC pin of the IR3521 does not have an open drain output since AMD SVID protocol does not
support slave clock stretching.
The IR3521 transitions from a 2-bit Boot VID mode to SVI mode upon assertion of PWROK. The SMBus send byte
protocol is used by the IR3521 VID-on-the-fly transactions. The IR3521 will wait until it detects a start bit which is
defined as an SVD falling edge while SVC is high. A 7bit address code plus one write bit (low) should then follow
the start bit. This address code will be compared against an internal address table and the IR3521 will reply with an
acknowledge ACK bit if the address is one of the three stored addresses otherwise the ACK bit will not be sent out.
The SVD pin is pulled low by the IR3521 to generate the ACK bit. Table 4 has the list of addresses recognized by
the IR3521.
The processor should then transmit the 8-bit data word immediately following the ACK bit. The first data bit (bit 7),
of the SVID data word, represents the Power State Indicator (PSI) bit which is passed on to the phase ICs via the
IR3521 PSI_L pin. PSI_L is pulled high by an internal 10K resistor to VCCL when data bit 7 of an SVID command
is high. A low, on this bit (bit 7), will pull the PSL_pin low and trigger all connected, predetermine, phase ICs to turn
off. If transitioning from one phase to multiple phases, the last phase IC, or returning phase IC, should be left on to
ensure the fastest possible clock frequency calibration. A shorter calibration time will help minimize droop at the
VDD output when leaving PSI_L mode. The remaining data bits SVID[6:0] select the desired VDACx regulation
voltage as defined in Table 3. The IR3521 replies again with an ACK bit once the data is received. If the received
data is not a VID-OFF command, the IR3521 immediately changes the DAC analog outputs to the new target.
VDAC1 and VDAC2 then slew to the new VID voltages. See Figure 12 for a send byte example.
Table 1 – 2-bit Boot VID codes Table 2 – VFIX mode 2 bit VID Codes
SVC SVD Output Voltage(V)
0 0 1.1
0 1 1.0
1 0 0.9
1 1 0.8
Figure 12 Send Byte Example
SVC SVD Output Voltage(V)
0 0 1.4
0 1 1.2
1 0 1.0
1 1 0.8
IR3521
Page 21 V3.03
Table 3 - AMD 7 BIT SVID CODES
SVID [6:0] Voltage (V) SVID [6:0] Voltage (V) SVID [6:0] Voltage (V) SVID [6:0] Voltage (V)
000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.5000
000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.5000
000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.5000
000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.5000
000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.5000
000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.5000
000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.5000
000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0110 0.5000
000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.5000
000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.5000
000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.5000
000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.5000
000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.5000
000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.5000
000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.5000
000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.5000
001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.5000
001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.5000
001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.5000
001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.5000
001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.5000
001_0101 1.2875 011_0101 0.8875 101_0101 0.5000 111_0101 0.5000
001_0110 1.2750 011_0110 0.8750 101_0110 0.5000 111_0110 0.5000
001_0111 1.2625 011_0111 0.8625 101_0111 0.5000 111_0111 0.5000
001_1000 1.2500 011_1000 0.8500 101_1000 0.5000 111_1000 0.5000
001_1001 1.2375 011_1001 0.8375 101_1001 0.5000 111_1001 0.5000
001_1010 1.2250 011_1010 0.8250 101_1010 0.5000 111_1010 0.5000
001_1011 1.2125 011_1011 0.8125 101_1011 0.5000 111_1011 0.5000
001_1100 1.2000 011_1100 0.8000 101_1100 0.5000 111_1100 OFF
001_1101 1.1875 011_1101 0.7875 101_1101 0.5000 111_1101 OFF
001_1110 1.1750 011_1110 0.7750 101_1110 0.5000 111_1110 OFF
001_1111 1.1625 011_1111 0.7625 101_1111 0.5000 111_1111 OFF
Table 4 - SVI Send Byte Address Table
SVI Address [6:0] + Wr Description
110xx100b
Set VID only on Output 1
110xx010b
Set VID only on Output 2
110xx110b Set VID on both Output 1 and Output 2
Note: ‘x’ in the above Table 4 means the bit could be either ‘1’ or ‘0’.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

IR3521MTRPBF

Mfr. #:
Buy IR3521MTRPBF
Manufacturer:
Infineon Technologies
Description:
Power Management Specialized - PMIC X-PHASE IR3521 AMD SVID CTRL IC
Lifecycle:
New from this manufacturer.
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