IR3521MTRPBF Datasheet IR3521MTRPBF | P7-P9

IR3521

Page 7 V3.03

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Soft Start and Delay

Start Delay Measure Enable to EAOUTx activation 1 2.9 3.5 ms

Start-up Time Measure Enable activation to PGOOD 3 8 13 ms

OC Delay Time V(IINx) – V(OCSETx) = 500 mV 85 170 325 us

SS/DELx to FBx Input Offset

Voltage

With FBx = 0V, adjust V(SS/DELx) until

EAOUTx drives high

0.7 1.4 1.9 V

Charge Current -30 -50 -70

A

OC Delay/VID Off Discharge

Currents

Note 1 47

A

Fault Discharge Current 2.5 4.5 6.5

A

Hiccup Duty Cycle I(Fault) / I(Charge) 7 10 12 uA/uA

Charge Voltage 3.5 3.9 4.2 V

Delay Comparator Threshold Relative to Charge Voltage, SS/DELx

rising Note 1

80 mV

Delay Comparator Threshold Relative to Charge Voltage, SS/DELx

falling Note 1

120 mV

Delay Comparator Hysteresis Note 1 40 mV

Discharge Comp. Threshold 150 200 300 mV

Over-Current Comparators

Input Offset Voltage 1V  V(OCSETx)  3.3V -35 0 35 mV

OCSET Bias Current

-5%

Vrosc(V)*100

0/Rosc(KΩ)

+5%

A

2048-4096 Count Threshold Adjust ROSC value to find threshold 16 k

1024-2048 Count Threshold Adjust ROSC value to find threshold 20 k

Error Amplifiers

VID  1V

-0.5 0.5

0.8V  VID < 1V -5 +5 mV

System Set-Point Accuracy

(Deviation from Table 1, 2, and

3 per test circuit in Figures 2A

& 2B)

0.5V  VID < 0.8V -8 +8 mV

Input Offset Voltage Measure V(FBx) – V(VDACx)). Note 2 -1 0 1 mV

FB1 Bias Current

-5%

Vrosc(V)*1000

/Rosc(KΩ)

+5%

A

FB2 Bias Current -1 0 1

A

DC Gain Note 1

100 110 135

Bandwidth Note 1

30 40 MHz

Slew Rate Note 1

5.5

12 20

V/s

Sink Current 0.4 0.85 1 mA

Source Current 5.0 8.5 12.0 mA

Maximum Voltage Measure V(VCCL) – V(EAOUTx) 500 780 950 mV

Minimum Voltage 120 250 mV

Open Voltage Loop Detection

Threshold

Measure V(VCCL) - V(EAOUT), Relative

to Error Amplifier maximum voltage.

125 300 600 mV

Open Voltage Loop Detection

Delay

Measure PHSOUT pulse numbers from

V(EAOUTx) = V(VCCL) to PGOOD = low.

8 Pulses

Enable Input

Blanking Time Noise Pulse < 100ns will not register an

ENABLE state change. Note 1

75 250 400 ns

VDAC References

Source Currents Includes I(OCSETx)

-8%

3050*Vrosc(V)

/ ROSC(kΩ)

+8%

A

Sink Currents Includes I(OCSETx)

-8%

2650*Vrosc(V)

/ ROSC(kΩ)

+8%

A

PGOOD Output

Under Voltage Threshold -

Voutx Decreasing

Reference to VDACx -365 -315 -265 mV

IR3521

Page 8 V3.03

Note 1: Guaranteed by design, but not tested in production Note 2: VDACx Outputs are trimmed to compensate for Error & Amp

Remote Sense Amp input offset.

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Under Voltage Threshold - Voutx

Increasing

Reference to VDACx -325 -275 -225 mV

Under Voltage Threshold Hysteresis 5 53 110 mV

Output Voltage I(PGOOD) = 4mA 150 300 mV

Leakage Current V(PGOOD) = 5.5V 0 10

A

VCCL Activation Threshold I(PGOOD) = 4mA, V(PGOOD) =

300mV

1.73 3.5 V

Over Voltage Protection (OVP) Comparators

Threshold at Power-up 1.60 1.73 1.83 V

Voutx Threshold Voltage Compare to V(VDACx)

220 260 285

OVP Release Voltage during Normal

Operation

Compare to V(VDACx) -20 3 25 mV

Threshold during Dynamic VID down 1.8 1.85 1.9 V

Dynamic VID Detect Comparator Threshold Note 1 25 50 75 mV

Propagation Delay to IIN Measure time from V(Voutx) >

V(VDACx) (250mV overdrive) to

V(IINx) transition to > 0.9 *

V(VCCL).

90 180 ns

OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) 0 1.2 V

OVP Power-up High Voltage V(VCCLDRV)=1.8V. Measure

V(VCCL)-V(ROSC/OVP)

0 0.2 V

Propagation Delay to OVP Measure time from V(Voutx) >

V(VDACx) (250mV overdrive) to

V(ROSC/OVP) transition to >1V.

150 300 nS

IIN Pull-up Resistance 5 15 

Open Sense Line Detection

Sense Line Detection Active Comparator

Threshold Voltage

150 200 250 mV

Sense Line Detection Active Comparator

Offset Voltage

V(Voutx) < [V(VOSENx+) –

V(LGND)] / 2

29 62.5 90 mV

VOSEN+ Open Sense Line Comparator

Threshold

Compare to V(VCCL) 86.5 89.0 91.5 %

VOSEN- Open Sense Line Comparator

Threshold

0.36 0.40 0.44 V

Sense Line Detection Source Currents V(Voutx) = 100mV 200 500 700 uA

VCCL Regulator Amplifier

Reference Feedback Voltage 1.15 1.2 1.25 V

VCCLFB Bias Current -1 0 1 uA

VCCLDRV Sink Current 10 40 mA

UVLO Start Threshold Compare to V(VCCL) 89.0 93.5 97.0 %

UVLO Stop Threshold Compare to V(VCCL) 81.0 85.0 89.0 %

Hysteresis Compare to V(VCCL) 7.0 8.25 9.5 %

ENABLE, PWROK Inputs

Threshold Increasing 1.3 1.65

1.9

Threshold Decreasing

0.8

0.99 1.2 V

Threshold Hysteresis 470 620 770 mV

Bias Current 0V  V(x)  3.5V, SVC not asserted -5 0 5 uA

PWROK VFIX Mode Threshold 3.3

(VCCL

+3.3)(V) / 2

General

VCCL Supply Current

3.5 10 15

IR3521

Page 9 V3.03

PHSOUT FREQUENCY VS RROSC CHART

PHSOUT FREQUENCY vs. RROSC

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

1500

1600

5 10152025303540455055

RROSC (KOhm)

Frequency (KHz)

Figure 2 - Phout Frequency vs. RROSC chart

System Fault Table

Response Open

Daisy

Open

Sense

Open

Voltage

UVLO

(VCCL)

Over

Voltage

Disable VID_OFF

SVID

Before

After

UVLO

(Vout)

Latch UV & EN Latch EN Fault Latch SS Latch No

Reset Recycle VCCL then Enable Recycle Enable SS discharge below 0.2V No

Outputs

Affected

Both Single Both Both Both Single Single Single

Disables

Yes

SS/DELx

Discharge

Yes No

Flags

PGood

Yes

Delays 32

Clock

Pulses

No 8

PHSOUT

Pulses

No No 250ns

Blanking

Time

No PHSOUT

Pulses*

SS/DELx

Discharge

Threshold

Additional

Flagged

Response

No Yes,

IINx and

Rosc pins

pulled-up to

VCCL

* Pulse number range depends on Rosc value selected (See Specifications Table)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45

IR3521MTRPBF

Mfr. #:

Buy IR3521MTRPBF

Manufacturer:

Infineon Technologies

Description:

Power Management Specialized - PMIC X-PHASE IR3521 AMD SVID CTRL IC

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IR3521MTRPBF