IR3521
Page 4 V3.03
PIN# PIN
SYMBOL
PIN DESCRIPTION
20 SS/DEL1 Programs output 1 startup and over current protection delay timing. Connect an
external capacitor to LGND to program.
21 IIN1 Output 1 average current input from the output 1 phase IC(s). This pin is also used
to communicate over voltage condition to phase ICs.
22 VDRP1 Output 1 Buffered IIN1 signal. Connect an external RC network to FB1 to program
converter output impedance.
23 ROSC/OVP Connect a resistor to LGND to program oscillator frequency and OCSET1, OCSET2,
FB1, FB2, VDAC1, and VDAC2 bias currents. Oscillator frequency equals switching
frequency per phase. The pin voltage is 0.6V during normal operation and higher
than 1.6V if over-voltage condition is detected.
24 PSI_L Digital output to communicate the systems power state to phase ICs PSI_L pin.
25 CLKOUT Clock output at switching frequency multiplied by phase number. Connect to CLKIN
pins of phase ICs.
26 PHSOUT Phase clock output at switching frequency per phase. Connect to PHSIN pin of the
first phase IC.
27 PHSIN Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
28 VCCL Output of the voltage regulator, and power input for clock oscillator circuitry. Connect
a decoupling capacitor to LGND. No external power rail connection is allowed.
29 VCCLFB Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by the resistor divider connected to VCCL.
30 VCCLDRV Output of the VCCL regulator error amplifier to control external transistor. The pin
senses 12V power supply through a resistor.
31 PGOOD Open collector output that drives low during startup and under any external fault
condition. And it monitors output voltages, if any of the voltage planes fall out of
spec, it will drive low. Connect external pull-up. ( Output voltage out of spec is
defined as 350mV to 240mV below VDAC voltage )
32 SVC SVC (Serial VID Clock) is an open drain output of the processor and input to
IR3521, requires an external bias voltage and should not be floated
EPAD LGND Local ground for internal circuitry and IC substrate connection.
IR3521
Page 5 V3.03
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied. All voltages are absolute voltages referenced to the
LGND pin.
Operating Junction Temperature……………..0 to 150
o
C
Storage Temperature Range………………….-65
o
C to 150
o
C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
Reflow Temperature…………………………….260
o
C
PIN # PIN NAME V
MAX
V
MIN
I
SOURCE
I
SINK
1 SVD 8V -0.3V 1mA 10mA
2 PWROK 8V -0.3V 1mA 1mA
3 ENABLE 3.5V -0.3V 1mA 1mA
4 IIN2 8V -0.3V 5mA 1mA
5 SS/DEL2 8V -0.3V 1mA 1mA
6 VDAC2 3.5V -0.3V 1mA 1mA
7 OCSET2 8V -0.3V 1mA 1mA
8 EAOUT2 8V -0.3V 25mA 10mA
9 FB2 8V -0.3V 1mA 1mA
10 VOUT2 8V -0.3V 5mA 25mA
11 VOSEN2+ 8V -0.5V 5mA 1mA
12 VOSEN2- 1.0V -0.5V 5mA 1mA
13 VOSEN1- 1.0V -0.5V 5mA 1mA
14 VOSEN1+ 8V -0.5V 5mA 1mA
15 VOUT1 8V -0.3V 5mA 25mA
16 FB1 8V -0.3V 1mA 1mA
17 EAOUT1 8V -0.3V 25mA 10mA
18 OCSET1 8V -0.3V 1mA 1mA
19 VDAC1 3.5V -0.3V 1mA 1mA
20 SS/DEL1 8V -0.3V 1mA 1mA
21 IIN1 8V -0.3V 5mA 1mA
22 VDRP1 8V -0.3V 35mA 1mA
23 ROSC/OVP 8V -0.3V 1mA 1mA
24 PSI_L VCCL+ 0.3V -0.3V 1mA 20mA
25 CLKOUT 8V -0.3V 100mA 100mA
26 PHSOUT 8V -0.3V 10mA 10mA
27 PHSIN 8V -0.3V 1mA 1mA
28 VCCL 8V -0.3V 1mA 20mA
29 VCCLFB 3.5V -0.3V 1mA 1mA
30 VCCLDRV 10V -0.3V 1mA 50mA
31 PGOOD VCCL + 0.3V -0.3V 1mA 20mA
32 SVC 8V -0.3V 1mA 1mA
EPAD LGND n/a n/a 20mA 1mA
IR3521
Page 6 V3.03
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V VCCL 7.5V, -0.3V VOSEN-x 0.3V, 0
o
C T
J
100
o
C, 7.75 k ROSC 50 k, CSS/DELx = 0.1uF
ELECTRICAL CHARACTERISTICS
The electrical characteristics table shows the spread of values guaranteed within the recommended operating conditions (unless
otherwise specified). Typical values (TYP) represent the median values, which are related to 25°C.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SVID Interface
Threshold Increasing 0.8025 0.90
0.9975
V
Threshold Decreasing
570
650 750 mV
SVC & SVD Input Thresholds
Threshold Hysteresis
150
250 400 mV
Bias Current 0V V(x) 3.5V, SVD not asserted -5 0 5 uA
SVD Low Voltage I(SVD)= 3mA 20 300 mV
SVD Fall Time, C
SVD
=400 pF 70-30% VDDIO, 1.425V VDDIO 1.9V,
1.7MHz operation, Note 1
20 40 160
ns
SVD Fall Time, C
SVD
=100 pF 3.4MHz operation
20 80
ns
Pulse width input filter Note 1
10
20 20
<100
ns
PSI_L OUTPUT
Output Voltage I(PSI_L) = 3mA 150 300 mV
Pull-up Resistance (to VCCL) 6 10 20 k
Oscillator
PHSOUT Frequency
-10% See
Figure 2
+10%
kHz
ROSC Voltage 0.57 0.600 0.630 V
CLKOUT High Voltage I(CLKOUT)= -10 mA, measure V(VCCL) –
V(CLKOUT).
1 V
CLKOUT Low Voltage I(CLKOUT)= 10 mA 1 V
PHSOUT High Voltage I(PHSOUT)= -1 mA, measure V(VCCL) –
V(PHSOUT)
1 V
PHSOUT Low Voltage I(PHSOUT)= 1 mA 1 V
PHSIN Threshold Voltage Compare to V(VCCL) 30 50 70 %
VDRP1 Buffer Amplifier
Input Offset Voltage V(VDRP1) – V(IIN1), 0.5V V(IIN) 3.3V
-8 0 8
mV
Source Current 0.5V V(IIN1) 3.3V 2 30 mA
Sink Current 0.5V V(IIN1) 3.3V 0.2 0.4 0.6 mA
Unity Gain Bandwidth Note 1 8 MHz
Slew Rate Note 1 4.7
V/s
IIN Bias Current -2 -0.2 1
A
Remote Sense Differential Amplifiers
Unity Gain Bandwidth Note 1 3.0 6.4 9.0 MHz
Input Offset Voltage 0.5V V(VOSENx+) - V(VOSENx-) 1.6V,
Note 2
-3 0 3 mV
Source Current 0.5V V(VOSENx+) - V(VOSENx-) 1.6V 0.5 1 1.7 mA
Sink Current 0.5V V(VOSENx+) - V(VOSENx-) 1.6V 2 12 18 mA
Slew Rate 0.5V V(VOSENx+) - V(VOSENx-) 1.6V 2 4 8 V/us
VOSEN+ Bias Current TBS V < V(VOSENx+) < 1.6V 30 50 uA
VOSEN- Bias Current -0.3V VOSENx- 0.3V, All VID Codes 30 50 uA
VOSEN+ Input Voltage Range V(VCCL)=7V 5.5 V
Low Voltage V(VCCL) =7V 250 mV
High Voltage V(VCCL) – V(VOUTx) 0.5 1 V

IR3521MTRPBF

Mfr. #:
Manufacturer:
Infineon Technologies
Description:
Power Management Specialized - PMIC X-PHASE IR3521 AMD SVID CTRL IC
Lifecycle:
New from this manufacturer.
Delivery:
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