LT3844
6
3844fc
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pin FuncTions
V
IN
(Pin 1): The V
IN
pin is the main supply pin and should
be decoupled to SGND with a low ESR capacitor located
close to the pin.
SHDN (Pin 2): The SHDN pin has a precision IC enable
threshold of 1.35V (rising) with 120mV of hysteresis. It is
used to implement an undervoltage lockout (UVLO) circuit.
See Applications Information section for implementing
a UVLO function. When the SHDN pin is pulled below
a transistor V
BE
(0.7V), a low current shutdown mode
is entered, all internal circuitry is disabled and the V
IN
supply current is reduced to approximately 9µA. Typical
pin input bias current is <10µA and the pin is internally
clamped to 6V.
C
SS
(Pin 3): The soft-start pin is used to program the
supply soft-start function. Use the following formula to
calculate C
SS
for a given output voltage slew rate:
C
SS
= 2µA(t
SS
/1.231V)
The pin should be left unconnected when not using the
soft-start function.
BURST_EN (Pin 4): The BURST_EN pin is used to enable
or disable Burst Mode operation. Connect the BURST_EN
pin to ground to enable the burst mode function. Connect
the pin to V
FB
or V
CC
to disable the Burst Mode function.
V
FB
(Pin 5): The output voltage feedback pin, V
FB
, is exter-
nally connected to the supply output voltage via a resistive
divider. The V
FB
pin is internally connected to the inverting
input of the error amplifier. In regulation, V
FB
is 1.231V.
V
C
(Pin 6): The V
C
pin is the output of the error amplifier
whose voltage corresponds to the maximum (peak) switch
current per oscillator cycle. The error amplifier is typically
configured as an integrator circuit by connecting an RC
network from the V
C
pin to SGND. This circuit creates the
dominant pole for the converter regulation control loop.
Specific integrator characteristics can be configured to
optimize transient response. When Burst Mode operation
is enabled (see Pin 4 description), an internal low imped
-
ance clamp on the V
C
pin is set at 100mV below the burst
threshold, which limits the negative excursion of the pin
voltage. Therefore, this pin cannot be pulled low with a
low impedance source. If the V
C
pin must be externally
manipulated, do so through a 1k series resistance.
SYNC (Pin 7): The SYNC pin provides an external clock
input for synchronization of the internal oscillator. R
SET
is set such that the internal oscillator frequency is 10%
to 25% below the external clock frequency. If unused the
SYNC pin is connected to SGND. For more information see
“Oscillator Sync” in the Applications Information section
of this data sheet.
f
SET
(Pin 8): The f
SET
pin programs the oscillator frequency
with an external resistor, R
SET
. The resistor is required
even when supplying external sync clock signal. See the
Applications Information section for resistor value selec
-
tion details.
SGND (Pin 9, 17): The SGND pin is the low noise ground
reference. It should be connected to the –V
OUT
side of the
output capacitors. Careful layout of the PCB is necessary
to keep high currents away from this SGND connection.
See the Applications Information section for helpful hints
on PCB layout of grounds.
SENSE
–
(Pin 10): The SENSE
–
pin is the negative input for
the current sense amplifier and is connected to the V
OUT
side of the sense resistor for step-down applications. The
sensed inductor current limit is set to 100mV across the
SENSE inputs.
SENSE
+
(Pin 11): The SENSE
+
pin is the positive input for
the current sense amplifier and is connected to the induc-
tor side of the sense resistor for step-down applications.
The sensed inductor current limit is set to
100mV
across
the SENSE inputs.
PGND (Pin 12): The PGND pin is the high current ground
reference for internal low side switch and the V
CC
regulator
circuit. Connect the pin directly to the negative terminal of
the V
CC
decoupling capacitor. See the Applications Informa-
tion section for helpful hints on PCB layout of grounds.
