Pin configuration STHDLS101T
10/26
Pin
number
Name Type Function
27 GND Power Ground
28 SCL_SINK Output
5 V DDC Clock I/O. Pulled-up by external termination
to 5 V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS pass-gate
29 SDA_SINK I/O
5V DDC Data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS pass-gate
30 HPD_SINK Input
Low-frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage high
indicates “plugged” state; voltage low indicates
“unplugged” state. HPD_SINK is pulled down by an
integrated 160KΩ pull-down resistor.
31 GND Power Ground
32 DDC_EN Input
Enables bias voltage to the DDC pass-gate level shifter
gates. (May be implemented as a bias voltage
connection to the DDC pass-gate themselves).
DDC_EN Pass-gate
0 V Disabled
3.3 V Enabled
33 VCC33 Power 3.3V±10% DC supply
34 FUNCTION3 Input
Used for polarity control of the HPD_SOURCE output.
When L, the HPD_SOURCE is an open-drain output
sand when H, the HPD_SOURCE is a buffered output
(O V to V
CC
)
35 FUNCTION4
Vendor-specific
control or test
pins
Function pins are to enable vendor-specific features or
test modes.
For normal operation, these pins are tied to GND or
VCC33.
For consistent interoperability, GND is the preferred
default connection for these signals
36 GND Power Ground
37 GND Power Ground
38 IN_D1- Input
Low-swing differential input from GMCH PCIE outputs.
IN_D1- makes a differential pair with IN_D1+.
39 IN_D1+ Input
Low-swing differential input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1-.
40 VCC33 Power 3.3 V±10% DC supply
41 IN_D2- Input
Low-swing differential input from GMCH PCIE outputs.
IN_D2- makes a differential pair with IN_D2+.
42 IN_D2+ Input
Low-swing differential input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2-.
Table 2. Pin description (continued)
Obsolete Product(s) - Obsolete Product(s)
