STHDLS101T Pin configuration
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3 Pin configuration
Figure 5. STHDLS101T pin configuration
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
25
26
27
28
29
30
31
32
33
34
35
36
GND
IN_D1+
IN_D2-
IN_D4+
OUT_D4+
GND
OUT_D2+
OUT_D2-
SDA_SINK
HPD_SINK
IN_D3+
VCC33
VCC33
GND
QFN-48
IN_D2+
IN_D3-
IN_D4-
FUNCTION4
FUNCTION3
VCC33
DDC_EN
OUT_D1+
VCC33
GND
SCL_SINK
GND
VCC33
OUT_D1-
GND
GND
1
2
3
4
5
6
9
7
8
10
11
12
GND
VCC
33
FUNCTION2
VCC
33
GND
SDA_
SOURCE
FUNCTION1
SCL_
SOU
RCE
REXT
GND
HPD_SOURCE
ANALOG2
OE_N
IN_D1-
OUT_D4-
VCC33
OUT_D3+
OUT_D3-
CS000118
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Pin configuration STHDLS101T
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3.1 Pin description
Table 2. Pin description
Pin
number
Name Type Function
1GND PowerGround
2 VCC33 Power 3.3V±10% DC supply
3 FUNCTION1
Vendor-specific
control or test
pins
Function pins are to enable vendor-specific features or
test modes.
For normal operation, these pins are tied to GND or
VCC33.
For consistent interoperability, GND is the preferred
default connection for these signals
4 FUNCTION2
Vendor-specific
control or test
pins
Function pins are to enable vendor-specific features or
test modes.
For normal operation, these pins are tied to GND or
VCC33.
For consistent interoperability, GND is the preferred
default connection for these signals
5GND PowerGround
6 REXT Analog
Connection to external resistor. Resistor value
specified by device manufacturer.
Acceptable connections to this pin are:
- Resistor to GND
- Resistor to 3.3V;
- NC (direct connections to V
CC
or GND are through a
0-Ù resistor for layout compatibility
7 HPD_SOURCE Output
Buffer from the 0 V to 5 V input signal. The output
buffer stage is configurable based on the FUNCTION3
pin settings as desribed in the table below:
FUNCTION3 HPD_SINK HPD_SOURCE
0Low
Open-drain,
connected an
external pull up to
the desired
supply
(normally 1 V)
0 High (5 V) Low (0 V)
1 Low (0 V) Low (0 V)
1 High (5 V) High (3 V)
8 SDA_SOURCE I/O
3.3 V DDC data I/O. Pulled-up by external termination
to 3.3 V. Connected to SDA_SINK through voltage-
limiting integrated NMOS pass-gate
9 SCL_SOURCE Input
3.3 V DDC clock I/O. Pulled-up by external termination
to 3.3 V. Connected to SCL_SINK through voltage-
limiting integrated NMOS pass-gate
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STHDLS101T Pin configuration
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Pin
number
Name Type Function
10 ANALOG2 Analog
Analog connection determined by vendor.
Acceptable connections to this pin are:
- Resistor or capacitor to GND
- Resistor or capacitor to 3.3 V
- Short to 3.3 V or to GND
- NC
11 VCC33 Power 3.3 V ±10% DC supply
12 GND Power Ground
13 OUT_D4+ Output
HDMI 1.3 compliant TMDS output.
OUT_D4+ makes a differential output signal with
OUT_D4-.
14 OUT_D4- Output
HDMI 1.3 compliant TMDS output.
OUT_D4- makes a differential output signal with
OUT_D4+.
15 VCC33 Power 3.3 V±10% DC supply
16 OUT_D3+ Output
HDMI 1.3 compliant TMDS output.
OUT_D3+ makes a differential output signal with
OUT_D3-.
17 OUT_D3- Output
HDMI 1.3 compliant TMDS output.
OUT_D3- makes a differential output signal with
OUT_D3+.
18 GND Power Ground
19 OUT_D2+ Output
HDMI 1.3 compliant TMDS output.
OUT_D2+ makes a differential output signal with
OUT_D2-.
20 OUT_D2- Output
HDMI 1.3 compliant TMDS output.
OUT_D2- makes a differential output signal with
OUT_D2+.
21 VCC33 Power 3.3 V±10% DC supply
22 OUT_D1+ Output
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.
23 OUT_D1- Output
HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.
24 GND Power Ground
25 OE_N Input
Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables chip
when unconnected.
OE_N
IN_D
termination
OUT_D Outputs
1 High-Z High-Z
050Ω Active
26 VCC33 Power 3.3 V±10% DC supply
Table 2. Pin description (continued)
Obsolete Product(s) - Obsolete Product(s)

STHDLS101TQTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Interface - Specialized AC coupled HDMI level shifter
Lifecycle:
New from this manufacturer.
Delivery:
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