1
DATASHEET
80V, 500mA, 3-Phase MOSFET Driver
HIP4086, HIP4086A
The HIP4086 and HIP4086A (referred to as the HIP4086/A)
are 3-phase N-channel MOSFET drivers. Both parts are
specifically targeted for PWM motor control. These drivers
have flexible input protocol for driving every possible switch
combination. The user can even override the shoot-through
protection for switched reluctance applications.
The HIP4086/A have a wide range of programmable dead
times (0.5µs to 4.5µs) which makes them very suitable for the
low frequencies (up to 100kHz) typically used for motor drives.
The only difference between the HIP4086 and the HIP4086A
is that the HIP4086A has the built-in charge pumps disabled.
This is useful in applications that require very quiet EMI
performance (the charge pumps operate at 10MHz). The
advantage of the HIP4086 is that the built-in charge pumps
allow indefinitely long on times for the high-side drivers.
To insure that the high-side driver boot capacitors are fully
charged prior to turning on, a programmable bootstrap refresh
pulse is activated when VDD is first applied. When active, the
refresh pulse turns on all three of the low-side bridge FETs
while holding off the three high-side bridge FETs to charge the
high-side boot capacitors. After the refresh pulse clears,
normal operation begins.
Another useful feature of the HIP4086/A is the programmable
undervoltage set point. The set point range varies from 6.6V to
8.5V.
Features
Independently drives 6 N-channel MOSFETs in 3-phase
bridge configuration
Bootstrap supply maximum voltage up to 95VDC with bias
supply from 7V to 15V
1.25A peak turn-off current
User programmable dead time (0.5µs to 4.5µs)
Bootstrap and optional charge pump maintain the high-side
driver bias voltage.
Programmable bootstrap refresh time
Drives 1000pF load with typical rise time of 20ns and fall
time of 10ns
Programmable undervoltage set point
Applications
Brushless Motors (BLDC)
•3-phase AC motors
Switched reluctance motor drives
•Battery powered vehicles
•Battery powered tools
Related Literature
AN9642, “HIP4086 3-Phase Bridge Driver Configurations
and Applications”
AN1829
, “HIP4086 3-Phase BLDC Motor Drive
Demonstration Board, User Guide”
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
CHARGE
PUMP
HIP4086 Yes
HIP4086A No
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. CHARGE PUMP OUTPUT CURRENT
Controller
AHO
CLO
BLO
ALO
CHO
BHO
CLI
BLI
ALI
CHI
BHI
AHI
CHS
AHS
BHS
CHB
AHB
BHB
VDD
RDEL
VDD
Speed
Brake
Battery
24V...48V
HIP4086/A
VSS
-60 -40 -20 0 20 40 60 80 100 120 140 160
200
150
100
50
0
JUNCTION TEMPERATURE (°C)
OUTPUT CURRENT (µA)
V
xHB
- V
xHS
= 10V
January 12, 2017
FN4220.11
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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All other trademarks mentioned are the property of their respective owners.
HIP4086, HIP4086A
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January 12, 2017
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Block Diagram (for clarity, only one phase is shown)
FIGURE 3. BLOCK DIAGRAM
RDEL 7
xLI 4
RFSH
9
UVLO
8
VDD 20
DIS
10
xHI
5
2µs Delay
REFRESH
PULSE
UNDERVOLTAGE
DETECTOR
10ns
DELAY
ADJUSTABLE
TURN-ON
DELAY
LEVEL
SHIFTER
CHARGE
PUMP*
xHO17
xHB
16
xHS
18
xLO21
VSS
6
VDD
100mV
VDD
*The charge pump is
permanently disabled
in the HIP4086A.
COMMON WITH
ALL PHASES
COMMON
WITH ALL
PHASES
COMMON WITH
ALL PHASES
COMMON WITH
ALL PHASES
EN
If the voltage on RDEL is less than 100mV, the
turn-on delay timers are disabled and the high and
low-side drivers can be turned on simultaneously.
If undervoltage is active or if
DIS is asserted, the high and
low-side drivers are turned off.
ADJUSTABLE
TURN-ON
DELAY
DELAY DISABLE
DRIVE ENABLE
Truth Table
INPUT OUTPUT
ALI, BLI, CLI AHI, BHI, CHI UV DIS RDEL ALO, BLO, CLO AHO, BHO, CHO
XXX1X00
XX1XX00
1 X 0 0 >100mV 1 0
0000X01
0100X00
1 0 0 0 <100mV 1 1
NOTE: X signifies that input can be either a “1” or “0”.
HIP4086, HIP4086A
3
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January 12, 2017
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Pin Configuration
HIP4086, HIP4086A
(24 LD PDIP, SOIC)
TOP VIEW
1
BHB
2
BHI
3
BLI
4
ALI
5
AHI
6
VSS
7
RDEL
8
UVLO
9
RFSH
10
DIS
11
CLI
12
CHI
24
BHO
23
BHS
22
BLO
21
ALO
20
VDD
19
CLO
18
AHS
17
AHO
16
AHB
15
CHS
14
CHO
13
CHB
Pin Descriptions
PIN NUMBER SYMBOL DESCRIPTION
16
1
13
AHB
BHB
CHB
(xHB)
High-Side Bias Connections. One external bootstrap diode and one capacitor are required for
each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB
pin.
18
23
15
AHS
BHS
CHS
(xHS)
High-Side Source Connections. Connect the sources of the high-side power MOSFETs to these
pins. The negative side of the bootstrap capacitors are also connected to these pins.
5
2
12
AHI
BHI
CHI
(xHI)
High-Side Logic Level Inputs. Logic at these three pins controls the three high-side output drivers,
AHO (Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI
is low, xHO is high. When xHI is high,
xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 7) to ground, the low-side
input of each phase will override the corresponding high-side input on that phase - see
Truth
Table” on page 2. If RDEL is tied to ground, dead time is disabled and the outputs follow the
inputs with no shoot-through protection. DIS (Pin 10) also overrides the high-side inputs. xHI
can
be driven by signal levels of 0V to 15V (no greater than V
DD
).
4
3
11
ALI
BLI
CLI
(xLI)
Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output drivers
ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower
inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL (Pin 7).
DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by signal
levels of 0V to 15V (no greater than V
DD
).
6 VSS Ground. Connect the sources of the low-side power MOSFETs to this pin.
7 RDEL Delay Time Set Point. Connect a resistor from this pin to V
DD
to set timing current that defines
the dead time between drivers - see Figure 19 on page 10
. All drivers turn off with minimal
delay, RDEL resistor prevents shoot-through by delaying the turn-on of all drivers. When RDEL is
tied to VSS, both upper and lowers can be commanded on simultaneously. While not necessary
in most applications, a decoupling capacitor of 0.1µF or smaller may be connected between
RDEL and VSS.
8 UVLO Undervoltage Set Point. A resistor can be connected between this pin and VSS to program the
undervoltage set point - see Figure 20 on page 10
. With this pin not connected, the under
voltage disable is typically 6.6V. When this pin is tied to VDD, the under voltage disable is
typically 6.2V.
9 RFSH Refresh Pulse Setting. An external capacitor can be connected from this pin to VSS to increase
the length of the start up refresh pulse - see Figure 18 on page 9
. If this pin is not connected, the
refresh pulse is typically 1.5µs.

HIP4086ABZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 80V 1.25A 3 PHS FL W V DRVR
Lifecycle:
New from this manufacturer.
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