HIP4086, HIP4086A
10
FN4220.11
January 12, 2017
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Functional Description
Input Logic
NOTE: When appropriate for brevity, input and output pins will be prefixed
with an “x” as a substitute for A, B, or C. For example, xHS refers to pins
AHS, BHS, and CHS.
The HIP4086/A are 3-phase bridge drivers designed specifically
for motor drive applications. Three identical half bridge sections,
A, B and C, can be controlled individually by their input pins, ALI,
AHI
, BLI, BHI, and CLI, CHI (xLI, xHI) or the 2 corresponding input
pins for each section can be tied together to form a PWM input
(xLI connected to xHI = xPWM). When controlling individual
inputs, the programmable dead time is optional but
shoot-through protection must then be incorporated in the timing
of the input signals. If the PWM mode is chosen, then the internal
programmable dead time must be used.
Shoot-Through Protection
Dead time, to prevent shoot-through, is implemented by delaying
the turn-on of the high-side and low-side drivers. The delay timers
are enabled if the voltage on the RDEL pin is greater than
100mV. The voltage on RDEL will be greater than 100mV for any
value of programming resistor in the specified range. If the
voltage on RDEL is less than 100mV, the delay timers are
disabled and no shoot-through protection is provided by the
internal logic of the HIP4086/A. When the dead time is to be
disabled, RDEL should be shorted to VSS.
Refresh Pulse
To insure that the boot capacitors are charged prior to turning on
the high-side drivers, a refresh pulse is triggered when DIS is low
or when the UV comparator transitions low (V
DD
is greater than
the programmed undervoltage threshold). Please refer to the
Block Diagram” on page 2. When triggered, the refresh pulse
turns on all of the low-side drivers (xLO = 1) and turns off all of
the high-side drivers (xHO = 0) for a duration set by a resistor tied
between RDEL and VSS. When xLO = 1, the low-side bridge FETs
charge the boot capacitors from VDD through the boot diodes.
FIGURE 19. DEAD TIME FIGURE 20. UNDERVOLTAGE THRESHOLD
FIGURE 21. I
xHS
LEAKAGE CURRENT
Typical Performance Curves (Continued)
JUNCTION TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100 120 140 160
0
2
4
6
DEAD TIME (µs)
RDEL = 100kΩ
RDEL = 10kΩ
JUNCTION TEMPERATURE (°C)
UNDERVOLTAGE SHUTDOWN/
-60 -40 -20 0 20 40 60 80 100 120 140 160
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
ENABLE VOLTAGE
ENABLE (50kΩ, UVLO TO GND)
TRIP (50k, UVLO TO GND)
ENABLE (UVLO OPEN)
TRIP (UVLO OPEN)
TRIP/ENABLE (0kΩ, UVLO TO V
DD
)
JUNCTION TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100 120 140 160
10
15
20
25
LEAKAGE CURRENT (µA)
V
xHS
= 80V
HIP4086, HIP4086A
11
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January 12, 2017
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Charge Pump
The internal charge pump of the HIP4086/A is used to maintain
the bias on the boot capacitor for 100% duty cycle. There is no
limit for the duration of this period. The user must understand
that this charge pump is only intended to provide the static bias
current of the high-side drivers and the gate leakage current of
the high-side bridge FETs. It cannot provide in a reasonable time,
the majority of the charge on the boot capacitor that is
consumed, when the xHO drivers source the gate charge to turn
on the high-side bridge FETs. The boot capacitors should be sized
so that they do not discharge excessively when sourcing the gate
charge. See
Application Information for methods to size the
boot capacitors.
The charge pump has sufficient capacity to source a worst-case
minimum of 40µA to the external load. The gate leakage current
of most power MOSFETs is about 100nA so there is more than
sufficient current to maintain the charge on the boot capacitors.
Because the charge pump current is small, a gate-to-source
resistor on the high-side bridge FETs is not recommended. When
calculating the leakage load on the outputs of xHS, also include
the leakage current of the boot capacitor. This is rarely a problem
but it could be an issue with electrolytic capacitors at high
temperatures.
Application Information
Selecting the Boot Capacitor Value
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is about 20 times the
gate charge of the driven power FET for approximately a 5% drop
in voltage after charge has been transferred from the boot
capacitor to the gate capacitance.
The following parameters shown in Table 2
are required to
calculate the value of the boot capacitor for a specific amount of
voltage droop when using the HIP4086/A (no charge pump). In
Table 2
, the values used are arbitrary. They should be changed to
comply with the actual application.
Equation 1
calculates the total charge required for the Period
duration. This equation assumes that all of the parameters are
constant during the Period duration. The error is insignificant if
Ripple is small.
If the gate-to-source resistor is removed (R
GS
is usually not
needed or recommended), then:
C
boot
= 0.33µF
These values of C
boot
will sustain the high-side driver bias during
Period with only a small amount of Ripple. But in the case of the
HIP4086, the charge pump reduces the value of C
boot
even
more. The specified charge pump current is a minimum of 40µA,
which is more than sufficient to source I
gate_leak
. Also, because
the specified charge pump current is in excess of what is needed
for I
HB
, the total charge required to be sourced by the boot
capacitor is shown by Equation 2.
Not only is the required boot capacitor smaller in value, there is
no restriction on the duration of Period.
TABLE 2.
V
DD
= 10V V
DD
can be any value between 7 and 15VDC.
V
HB
= V
DD
- 0.6V
= V
HO
High-side driver bias voltage (V
DD
- boot diode
voltage) referenced to V
HS
.
Period = 1ms This is the longest expected switching period.
I
HB
= 100µA Worst case high-side driver current when
xHO = high (this value is specified for V
DD
= 12V
but the error is not significant).
R
GS
= 100kΩ Gate-to-source resistor (usually not needed).
Ripple = 5% Desired ripple voltage on the boot capacitor
(larger ripple is not recommended).
I
gate_leak
= 100nA From the FET vendor’s datasheet.
Qgate80V = 64nC From Figure 22
.
Q
C
Q
gate80V
= Period (I
HB
V
HO
R
GS
I
gate_leak
+ )++
(EQ. 1)
C
boot
Q
C
= Ripple
VDD
C
boot
0.52F=
Q
C
Q
gate80V
= orC
boot
0.13F=
(EQ. 2)
FIGURE 22. TYPICAL GATE VOLTAGE vs GATE CHARGE
HIP4086, HIP4086A
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Typical Application Circuit
Figure 23 is an example of how the HIP4086 and HIP4086A
3-phase drivers can be applied to drive a 3-phase motor.
Depending on the application, the switching speed of the bridge
FETs can be reduced by adding series connected resistors
between the xHO outputs and the FET gates. Gate-to-source
resistors are recommended on the low-side FETs to prevent
unexpected turn-on of the bridge should the bridge voltage be
applied before V
DD
. Gate-to-source resistors on the high-side
FETs are not usually required if low-side gate-to-source resistors
are used. If relatively small gate-to-source resistors are used on
the high-side FETs, be aware that they will load the charge pump
of the HIP4086 negating the ability of the charge pump to keep
the high-side driver biased during very long periods.
An important operating condition that is frequently overlooked by
designers is the negative transient on the xHS pins that occurs
when the high-side bridge FET turns off. The absolute maximum
transient allowed on the xHS pin is -6V but it is wise to minimize
the amplitude to lower levels. This transient is the result of the
parasitic inductance of the low-side drain-to-source conductor on
the PCB. Even the parasitic inductance of the low-side FET
contributes to this transient.
When the high-side bridge FET turns off, because of the inductive
characteristics of a motor load, the current that was flowing in
the high-side FET (blue) must rapidly commutate to flow through
the low-side FET (red). The amplitude of the negative transient
impressed on the xHS node is (di/dt x L) where L is the total
parasitic inductance of the low-side FET drain-to-source path and
di/dt is the rate at which the high-side FET is turned off. With the
increasing power levels of new generation motor drives,
clamping this transient becomes more and more significant for
the proper operation of the HIP4086/A.
There are several ways of reducing the amplitude of this
transient. If the bridge FETs are turned off more slowly to reduce
di/dt, the amplitude will be reduced but at the expense of more
switching losses in the FETs. Careful PCB design will also reduce
the value of the parasitic inductance. However, these two
solutions by themselves may not be sufficient. Figure 24
illustrates a simple method for clamping the negative transient.
Two series connected, fast PN junction, 1A diodes are connected
between xHS and VSS as shown. It is important that the
components be placed as close as possible to the xHS and VSS
pins to minimize the parasitic inductance of this current path.
Two series connected diodes are required because they are in
parallel with the body diode of the low-side FET. If only one diode
is used for the clamp, it will conduct some of the negative load
current that is flowing in the low-side FET. In severe cases, a
small value resistor in series with the xHS pin as shown, will
further reduce the amplitude of the negative transient.
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because xHS node is floating up toward the bridge bias voltage.
The absolute maximum voltage rating for the xHS node does
need to be observed when the positive transient occurs.
FIGURE 23. TYPICAL APPLICATION CIRCUIT
FIGURE 24. BRIDGE WITH PARASITIC INDUCTANCES
VSS
xHS
xLO
xHO
INDUCTIVE
LOAD
+
-
+
-

HIP4086ABZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 80V 1.25A 3 PHS FL W V DRVR
Lifecycle:
New from this manufacturer.
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