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HIP4086ABZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
HIP4086, HIP4086A
4
FN4220.11
January 12, 2017
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10 DIS Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides
all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can be driven
by signal levels of 0V to 15V (no greater than V
DD
).
17
24
14
AHO
BHO
CHO
(xHO)
High-Side Outputs. Connect to the gates of the high-side power MOSFETs in each phase.
20 VDD Positive Supply. Decouple this pin to VSS (Pin 6).
21
22
19
ALO
BLO
CLO
(xLO)
Low-Side Outputs. Connect the gates of the low-side power MOSFETs to these pins.
NOTE: x = A, B or C.
Pin Descriptions (Continued)
PIN NUMBER SYMBOL DESCRIPTION
Ordering Information
PART NUMBER
(Note 3
)
PART
MARKING
TEMP RANGE
(°C)
CHARGE
PUMP PACKAGE
PKG.
DWG. #
HIP4086AB (Note 1
) HIP4086AB -40 to +125 Yes 24 Ld SOIC M24.3
HIP4086ABZ (Notes 1, 2) HIP4086ABZ -40 to +125 Yes 24 Ld SOIC (RoHS Compliant) M24.3
HIP4086APZ (Note 2
) HIP4086APZ -40 to +125 Yes 24 Ld PDIP (RoHS Compliant) E24.3
HIP4086AABZ (Notes 1
, 2) HIP4086AABZ -40 to +125 No 24 Ld SOIC (RoHS Compliant) M24.3
HIP4086DEMO1Z HIP4086 Demonstration Board
NOTES:
1. Add “T”, suffix for 1k unit tape and reel option. Please refer to TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for HIP4086
, HIP4086A. For more information on MSL, please see Technical
Brief TB363
.
HIP4086, HIP4086A
5
FN4220.11
January 12, 2017
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Absolute Maximum Ratings (Note 7) Thermal Information
Supply Voltage, V
DD
Relative to GND. . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic Inputs (xLI, xHI
) . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to V
DD
+ 0.3V
Voltage on xHS . . . . . . . . . . . . . . -6V (Transient) to 85V (-40
°C to +150°C)
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
xHS
- 0.3V) to V
xHS
+V
DD
Voltage on xLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
SS
- 0.3V) to V
DD
+0.3V
Voltage on xHO . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
xHS
- 0.3V) to V
xHB
+0.3V
Phase Slew Rate (on xHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Maximum Recommended Operating
Conditions
Supply Voltage, V
DD
Relative to GND. . . . . . . . . . . . . . . . . . . . . . . 7V to 15V
Logic Inputs (xLI, xHI
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS + VDD
Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
RDEL range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10kΩ to 100kΩ
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
SOIC Package (Notes 4
, 6) . . . . . . . . . . . . . 75 22
SOIC Package HIP4086AABZ
(Notes 5, 6) 51 22
PDIP* Package (Notes 4
, 6) . . . . . . . . . . . . 70 29
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
*Pb-free PDIPs can be used for through-hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For
JC
, the “case temp” location is taken at the package top center.
7. Replace x with A, B, or C.
DC Electrical Specifications V
DD
= V
xHB
= 12V, V
SS
= V
xHS
= 0V, R
DEL
= 20k, R
UV
= , Gate Capacitance (C
GATE
) = 1000pF, unless
otherwise specified. Boldface limits apply across the operating junction temperature range, -40°C to +150°C.
PARAMETER TEST CONDITIONS
T
J
= +25°C T
J
= -40°C TO +150°C
UNIT
MIN
(Note 9
)TYP
MAX
(Note 9)
MIN
(Note 9)
MAX
(Note 9)
SUPPLY CURRENTS
V
DD
Quiescent Current xHI = 5V, xLI = 5V (HIP4086) 2.7 3.4 5.1 1.96 5.3 mA
xHI
= 5V, xLI = 5V (HIP4086A) 2.3 2.8 3.1 1.8 3.3 mA
V
DD
Operating Current f = 20kHz, 50% Duty Cycle (HIP4086) 5.4 8.25 13 4 13.5 mA
f = 20kHz, 50% Duty Cycle (HIP4086A) 3.1 4.0 4.6 2.7 5.1 mA
xHB On Quiescent Current xHI
= 0V (HIP4086) - 40 110 - 140 µA
xHI
= 0V (HIP4086A) - 90 115 - 225 µA
xHB Off Quiescent Current xHI
= V
DD
(HIP4086) 0.6 0.8 1.3 0.5 1.4 mA
xHI
= V
DD
(HIP4086A) 0.8 1.0 1.2 0.7 1.25 mA
xHB Operating Current f = 20kHz, 50% Duty Cycle (HIP4086) 0.7 0.9 1.3 - 2.0 mA
f = 20kHz, 50% Duty Cycle (HIP4086A) 0.8 0.9 1.1 - 1.25 mA
xHB, xHS Leakage Current V
xHS
= 80V, V
xHB
= 93V 7 30 45 - 50 µA
Charge Pump, HIP4086 Only, (Note 8
)
Q
PUMP
Output Voltage No Load 11 12.5 14.6 10 14.75 V
Q
PUMP
Output Current V
xHS
= 12V, V
xHB
= 22V 40 100 160 - 185 µA
UNDERVOLTAGE PROTECTION
V
DD
Rising Undervoltage Threshold R
UV
open 6.2 7.1 8.0 6.1 8.1 V
V
DD
Falling Undervoltage Threshold R
UV
open 5.75 6.6 7.5 5.6 7.6 V
Minimum Undervoltage Threshold R
UV
= V
DD
5 6.2 6.8 4.8 6.9 V
HIP4086, HIP4086A
6
FN4220.11
January 12, 2017
Submit Document Feedback
INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS
Low Level Input Voltage - - 1.0 -0.8V
High Level Input Voltage 2.5 - - 2.7 - V
Input Voltage Hysteresis - 35 - --mV
Low Level Input Current V
IN
= 0V -60 -100 -155 -55 -165 µA
High Level Input Current V
IN
= 5V -1 - +1 -10 +10 µA
GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO
Low Level Output Voltage (V
OUT
- V
SS
)I
SINKING
= 30mA - 100 - -210mV
Peak Turn-On Current V
OUT
= 0V 0.3 0.5 0.7 -1.0A
NOTES:
8. The specified charge pump current is the total amount available to drive external loads across xHO and xHS.
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
AC Electrical Specifications V
DD
= V
xHB
= 12V, V
SS
= V
xHS
= 0V, C
GATE
= 1000pF, R
DEL
= 10k, unless otherwise specified. Boldface
limits apply across the operating junction temperature range, -40°C to +150°C.
PARAMETER TEST CONDITIONS
T
J
= +25°C T
J
= -40°C TO +150°C
UNIT
MIN
(Note 9
)TYP
MAX
(Note 9)
MIN
(Note 9)
MAX
(Note 9)
TURN-ON DELAY AND PROPAGATION DELAY
Dead Time (Figure 4
)R
DEL
= 100kΩ 34.57.2 38µs
R
DEL
= 10kΩ 0.38 0.5 0.75 0.3 0.8 µs
Dead Time Channel Matching R
DEL
= 10kΩ - 7 15 - 20 %
Lower Turn-Off Propagation Delay
(xLI to xLO Turn-Off) (Figures 4
or 5)
No load - 30 55 - 75 ns
Upper Turn-Off Propagation Delay
(xHI
to xHO Turn-Off) (Figures 4 or 5)
No load - 75 110 - 135 ns
Lower Turn-On Propagation Delay
(xLI to xLO Turn-On) (Figures 4
or 5)
No load - 45 82 - 100 ns
Upper Turn-On Propagation Delay
(xHI
to xHO Turn-On) (Figures 4 or 5)
No load - 65 110 - 158 ns
Rise Time C
GATE
= 1000pF - 20 40 - 60 ns
Fall Time C
GATE
= 1000pF - 10 20 - 40 ns
Disable
Lower Turn-Off Propagation Delay
(DIS
to xLO turn-off) (Figure 6)
-5580 - 104 ns
Disable
Upper Turn-Off Propagation Delay
(DIS
to xHO turn-off) (Figure 6)
-80116 - 147 ns
Disable to Lower Turn-On Propagation Delay
(DIS
to xLO turn-on) (Figure 6)
-5585 - 120 ns
Disable
to Upper Turn-On Propagation Delay
(DIS
to xHO turn-on) (Figure 6)
R
DEL
= 10kΩ, C
RFSH
open
-2.0- - - µs
DC Electrical Specifications V
DD
= V
xHB
= 12V, V
SS
= V
xHS
= 0V, R
DEL
= 20k, R
UV
= , Gate Capacitance (C
GATE
) = 1000pF, unless
otherwise specified. Boldface limits apply across the operating junction temperature range, -40°C to +150°C. (Continued)
PARAMETER TEST CONDITIONS
T
J
= +25°C T
J
= -40°C TO +150°C
UNIT
MIN
(Note 9
)TYP
MAX
(Note 9)
MIN
(Note 9)
MAX
(Note 9)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

HIP4086ABZ

Mfr. #:
Buy HIP4086ABZ
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 80V 1.25A 3 PHS FL W V DRVR
Lifecycle:
New from this manufacturer.
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