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ISL6537CRZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15
10
FN9142.6
July 18, 2007
will immediately shut down when the Fault Counter reaches
a count of 5 at any other time.
The 16384 counts that are required to reset the Fault Reset
Counter represent 8 soft-start cycles, as one soft-start cycle
is 2048 clock cycles. This allows the ISL6537 to attempt at
least one full soft-start sequence to restart the faulted
regulators.
When attempting to restart a faulted regulator, the ISL6537
will follow the preset start up sequencing. If a regulator is
already in regulation, then it will not be affected by the start
up sequencing.
V
DDQ
Overcurrent Protection
The overcurrent function protects the switching converter from
a shorted output by using the upper MOSFET on-resistance,
r
DS(ON)
, to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
OCSET
)
programs the overcurrent trip level (see Typical Application
diagrams on pages 3 and 4). An internal 20μA (typical) current
sink develops a voltage across R
OCSET
that is referenced to
the converter input voltage. When the voltage across the
upper MOSFET (also referenced to the converter input
voltage) exceeds the voltage across R
OCSET
, the overcurrent
function initiates a soft-start sequence. The initiation of soft-
start may affect other regulators. The V
TT_DDR
regulator is
directly affected as it receives it’s reference and input from
V
DDQ
.
The overcurrent function will trip at a peak inductor current
(I
PEAK)
determined by:
where I
OCSET
is the internal OCSET current source (20μA
typical). The OC trip point varies mainly due to the MOSFET
r
DS(ON)
variations. To avoid overcurrent tripping in the
normal operating load range, find the R
OCSET
resistor from
the equation above with:
1. The maximum r
DS(ON)
at the highest junction
temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine I
PEAK
for
,
where ΔI is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R
OCSET
to smooth the voltage across
R
OCSET
in the
presence of switching noise on the input voltage.
Thermal Protection (S0/S3 State)
If the ISL6537 IC junction temperature reaches a nominal
temperature of +140°C, all regulators will be disabled. The
ISL6537 will not re-enable the outputs until the junction
temperature drops below +110°C and either the bias voltage
is toggled in order to initiate a POR or the SLP_S5 signal is
forced LOW and then back to HIGH.
Shoot-Through Protection
A shoot-through condition occurs when both the upper and
lower MOSFETs are turned on simultaneously, effectively
shorting the input voltage to ground. To protect from a shoot-
through condition, the ISL6537 incorporates specialized
circuitry on the V
DDQ
regulator which insures that
complementary MOSFETs are not ON simultaneously.
The adaptive shoot-through protection utilized by the V
DDQ
regulator looks at the lower gate drive pin, LGATE, and the
upper gate drive pin, UGATE, to determine whether a
MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the other MOSFET is
allowed to turned ON. This method allows the V
DDQ
regulator to both source and sink current.
Since the voltage of the MOSFET gates are being measured
to determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing
such measures. Doing so may interfere with the shoot-
through protection.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
250kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes these
voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in the ISL6537
switching converter. The switching components are the most
I
PEAK
I
OCSET
x R
OCSET
r
DS ON()
-----------------------------------------------------=
(EQ. 3)
I
PEAK
I
OUT MAX()
ΔI()
2
----------
+>
ISL6537
11
FN9142.6
July 18, 2007
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 2
shows the connections of the critical components in the
converter. Note that capacitors C
IN
and C
OUT
could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal V
TT
LDO, the ground pad, pin 29, should be connected to the
internal ground plane through at least four vias. This allows
the heat to move away from the IC and also ties the pad to
the ground plane through a low impedance path.
The switching components should be placed close to the
ISL6537 first. Minimize the length of the connections
between the input capacitors, C
IN
, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 3 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The error
amplifier output (V
E/A
) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
IN
at the PHASE node. The
PWM wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage ΔV
OSC
.
V
DDQ
5VSBY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
L
1
C
OUT1
C
IN
5VDUAL
KEY
COMP
ISL6537
UGATE
R
4
R
2
C
BP
FB
DRIVE3
5VSBY
FIGURE 2. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
R
1
V
GMCH
FB3
C
2
VIA CONNECTION TO GROUND PLANE
C
OUT4
LOAD
LOAD
Q
1
R
5
R
6
PHASE
R
3
C
3
C
1
Q
2
12V
ATX
C
BP
GNDP
P12V
Q
4
LGATE
VDDQ(2)
VTT(2)
C
OUT2
LOAD
V
DDQ
V
TT
GND PAD
DRIVE2
V
TT_GMCH/CPU
FB2
C
OUT4
LOAD
R
7
R
8
Q
5
DRIVE4
FB4
C
OUT3
Q
3
REFADJ4
ISL6537
12
FN9142.6
July 18, 2007
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6537) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
Figure 4 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 4. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
P2
with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 4 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Output Voltage Selection
The output voltage of the all the external voltage regulators
converter can be programmed to any level between their
individual input voltage and the internal reference, 0.8V. An
external resistor divider is used to scale the output voltage
relative to the reference voltage and feed it back to the
inverting input of the error amplifier, refer to the Typical
Application on page 3.
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
V
DDQ
REFERENCE
L
O
C
O
ESR
V
IN
ΔV
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
1
C
2
COMP
V
DDQ
FB
Z
FB
ISL6537
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
R
4
V
DDQ
0.8 1
R
1
R
4
-------+
⎝⎠
⎜⎟
⎛⎞
×=
F
LC
1
2π x L
O
x C
O
-------------------------------------------=
F
ESR
1
2π x ESR x C
O
--------------------------------------------=
(EQ. 4)
F
Z1
1
2π x R
2
x C
1
------------------------------------=
F
Z2
1
2π x R
1
R
3
+() x C
3
-------------------------------------------------------=
F
P1
1
2π x R
2
x
C
1
x C
2
C
1
C
2
+
----------------------
⎝⎠
⎜⎟
⎛⎞
---------------------------------------------------------=
F
P2
1
2π x R
3
x C
3
------------------------------------=
(EQ. 5)
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M1M100K10K1K10010
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
F
LC
F
ESR
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
20LOG
(V
IN
/ΔV
OSC
)
MODULATOR
GAIN
(R
2
/R
1
)
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP
GAIN
ISL6537
P1-P3P4-P6P7-P9P10-P12P13-P15

ISL6537CRZ-T

Mfr. #:
Buy ISL6537CRZ-T
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 4-IN-1 DDR/CHIPSETG W/DL-STAGE GMCH CORE
Lifecycle:
New from this manufacturer.
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