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ISL6537CRZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15
4
FN9142.6
July 18, 2007
Absolute Maximum Ratings Thermal Information
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14V
Absolute Boot Voltage, V
BOOT
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, V
BOOT
- V
PHASE
. . . . . . . . 7.0V (DC)
8.0V (<10ns Pulse Width, 10μJ)
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
Thermal Resistance
θ
JA
(°C/W) θ
JC
(°C/W)
QFN Package (Notes 1, 2) . . . . . . . . . 32 5
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current I
CC_S0
S3# and S5# HIGH, UGATE/LGATE Open 5.50 7.00 8.00 mA
I
CC_S5
S5# LOW, S3# Don’t Care, UGATE/LGATE
Open
- 700 850 μA
POWER-ON RESET
Rising 5VSBY POR Threshold 4.10 - 4.45 V
Falling 5VSBY POR Threshold 3.60 - 3.95 V
Rising P12V POR Threshold 10.0 - 10.5 V
Falling P12V POR Threshold 8.80 - 9.75 V
OSCILLATOR AND SOFT-START
PWM Frequency f
OSC
220 250 280 kHz
Ramp Amplitude ΔV
OSC
-1.5- V
Soft-Start Interval t
SS
6.5 8.2 9.5 ms
REFERENCE VOLTAGE
Reference Voltage V
REF
- 0.800 - V
System Accuracy -2.0 - +2.0 %
V
DDQ
PWM CONTROLLER ERROR AMPLIFIER
DC Gain (Note 3) - 80 - dB
Gain-Bandwidth Product GBWP (Note 3) 15 - - MHz
Slew Rate SR (Note 3) - 6 - V/μs
CONTROL I/O (S3# and S5#)
Low Level Input Threshold 0.75 - - V
High Level Input Threshold --2.2V
ISL6537
5
FN9142.6
July 18, 2007
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source I
GATE
--0.8- A
UGATE and LGATE Sink I
GATE
-0.8- A
VTT REGULATOR
Upper Divider Impedance R
U
-2.5- kΩ
Lower Divider Impedance R
L
-2.5- kΩ
VREF_OUT Buffer Source Current I
VREF_OUT
--2mA
Maximum V
TT
Load Current I
VTT_MAX
Periodic load applied with 30% duty cycle
and 10ms period using
ISL6537_6506EVAL1 evaluation board
(see Application Note AN1123)
-3 - 3 A
LINEAR REGULATORS
DC GAIN (Note 3) - 80 - dB
Gain Bandwidth Product GBWP (Note 3) 15 - - MHz
Slew Rate SR (Note 3) - 6 - V/μs
DRIVEn High Output Voltage DRIVEn unloaded 9.75 10.0 - V
DRIVEn Low Output Voltage - 0.16 0.50 V
DRIVEn High Output Source Current V
FB
= 770mV; V
DRIVEn
= 0V - 1.7 - mA
DRIVEn Low Output Sink Current V
FB
= 830mV; V
DRIVEn
= 10V - 1.2 - mA
VIDPGD
V
TT_GMCH/CPU
Rising Threshold S0 0.725 0.74 - V
V
TT_GMCH/CPU
Falling Threshold S0 - 0.70 0.715 V
PROTECTION
OCSET Current Source I
OCSET
18 20 22 μA
V
TT_DDR
Current Limit (Note 3) -3.3 - 3.3 A
V
DDQ
OV Level V
FB
/V
REF
S0/S3 - 115 - %
V
DDQ
UV Level V
FB
/V
REF
S0/S3 - 75 - %
V
TT_DDR
OV Level V
TT
/V
VREF_IN
S0 - 115 - %
V
TT_DDR
UV Level V
TT
/V
VREF_IN
S0 - 85 - %
V
GMCH
UV Level V
FB4
/V
REF
S0 - 75 - %
V
TT_GMCH/CPU
UV Level V
FB2
/V
REF
S0 - 75 - %
Thermal Shutdown Limit T
SD
(Note 3) - 140 - °C
NOTE:
3. Limits should be considered typical and are not production tested.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ISL6537
6
FN9142.6
July 18, 2007
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6537. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6537 enters a reduced
power mode and draws less than 1mA (I
CC_S5
) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1μF capacitor.
P12V (Pin 3)
The V
TT
regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6537 provide the return path
for the V
TT
LDO, and switching MOSFET gate drivers. High
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
LGATE (Pin 28)
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
FB (Pin 15) and COMP (Pin 16)
The V
DDQ
switching regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. The V
DDQ
output voltage is set by an external
resistor divider connected to FB. With a properly selected
divider, V
DDQ
can be set to any voltage between the power
rail (reduced by converter losses) and the 0.8V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The FB pin is also monitored for under and overvoltage
events.
PHASE (Pin 24)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
OCSET (Pin 22)
Connect a resistor (R
OCSET
) from this pin to the drain of the
upper MOSFET. R
OCSET
, an internal 20μA current source
(I
OCSET
), and the upper MOSFET on-resistance (r
DS(ON)
)
set the converter overcurrent (OC) trip point according to the
following equation:
An overcurrent trip cycles the soft-start function.
VDDQ (Pins 7, 8)
The VDDQ pins should be connected externally together to
the regulated V
DDQ
output. During S0/S1 states, the VDDQ
pins serve as inputs to the V
TT
regulator and to the V
TT
Reference precision divider.
DDR_VTT (Pins 5, 6)
The DDR_VTT pins should be connect externally together.
During S0/S1 states, the DDR_VTT pins serve as the
outputs of the V
TT
linear regulator. During S3 state, the V
TT
regulator is disabled.
DDR_VTTSNS (Pin 9)
VTTSNS is used as the feedback for control of the V
TT
linear
regulator. Connect this pin to the V
TT
output at the physical
point of desired regulation.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of V
TT
and also acts as the
reference voltage for the V
TT
linear regulator. It is
recommended that a minimum capacitance of 0.1μF is
connected between V
DDQ
and VREF_OUT and also
between VREF_OUT and ground for proper operation.
VREF_IN (Pin 14)
A capacitor, C
SS
, connected between VREF_IN and ground
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (R
U
||R
L
), sets the
time constant for the start up ramp when transitioning from
S3/S4/S5 to S0/S1/S2.
The minimum value for C
SS
can be found through the
following equation:
The calculated capacitance, C
SS
, will charge the output
capacitor bank on the V
TT
rail in a controlled manner without
reaching the current limit of the V
TT
LDO.
I
PEAK
I
OCSET
xR
OCSET
r
DS ON()
-------------------------------------------------=
(EQ. 1)
C
SS
C
VTTOUT
V
DDQ
⋅
10 2A R
U
R
L
||
⋅⋅
------------------------------------------------
>
(EQ. 2)
ISL6537
P1-P3P4-P6P7-P9P10-P12P13-P15

ISL6537CRZ-T

Mfr. #:
Buy ISL6537CRZ-T
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 4-IN-1 DDR/CHIPSETG W/DL-STAGE GMCH CORE
Lifecycle:
New from this manufacturer.
Delivery:
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