9
FN9142.6
July 18, 2007
The digital soft-start for the PWM regulator is accomplished by
clamping the error amplifier reference input to a level
proportional to the internal digital soft-start voltage. As the soft-
start voltage slews up, the PWM comparator generates PHASE
pulses of increasing width that charge the output capacitor(s).
This method provides a rapid and controlled output voltage rise.
The linear regulators, with the exception of the internal
V
TT_DDR
LDO, are soft-started in a similar manner. The
error amplifier reference is clamped to the internal digital
soft-start voltage. As the soft-start voltage ramps up, the
respective DRIVE pin voltages increase, thus enhancing the
N-MOSFETs and charging the output capacitors in a
controlled manner.
At time t
3
, the V
DDQ_DDR
and upper V
GMCH
LDO output
rails are in regulation and the lower V
GMCH
LDO is soft-
started. At time t
4
, the V
GMCH
rail is in regulation and the
V
TT_GMCH/CPU
linear regulator is soft-started. At time t
5
,
the V
TT_GMCH/CPU
rail is in regulation and the V
TT_DDR
internal regulator is soft-started.
The V
TT_DDR
LDO soft-starts in a manner unlike the other
regulators. When the V
TT_DDR
regulator is disabled, the
reference is internally shorted to the V
TT_DDR
output. This
allows the termination voltage to float during the S3 sleep
state. When the ISL6537 enables the V
TT_DDR
regulator or
enters S0 state from a sleep state, this short is released and
the internal divide down resistors which set the V
TT_DDR
voltage to 50% of V
DDQ_DDR
will provide a controlled
voltage rise on the capacitor that is tied to the VREF_IN pin.
The voltage on this capacitor is the reference for the
V
TT_DDR
regulator and the output will track it as it settles to
50% of the V
DDQ
voltage. The combination of the internal
resistors and the V
REF_IN
capacitor will determine the rise
time of the V
TT_DDR
regulator (see the Functional Pin
Description section for proper sizing of the VREF_IN
capacitor).
At time t
6
, a full soft-start cycle has passed from the time that
the V
TT_DDR
regulator was enabled. At this time the
VIDPGD comparator is enabled. Once enabled if the
V
TT_GMCH/CPU
output is within regulation, the VIDPGD pin
will be forced to a high impedance state.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6537 will disable all the regulators except for the V
DDQ
regulator, which is continually supplied by the 5VDUAL rail.
VIDPGD will also transition LOW. When V
TT
is disabled, the
internal reference for the V
TT
regulator is internally shorted
to the V
TT
rail. This allows the V
TT
rail to float. When
floating, the voltage on the V
TT
rail will depend on the
leakage characteristics of the memory and MCH I/O pins. It
is important to note that the V
TT
rail may not bleed down to
0V. Figure 1 shows how the individual regulators are
affected by the S3 state at time t
7
.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the ISL6537
will initiate the soft-start sequence. This sequence is very
similar to the mechanical start soft-start sequencing. The
transition from S3 to S0 is represented in Figure 1 between
times t
8
and t
14
.
At time t
8
, the SLP_S3 signal transitions HIGH. This enables
the ATX, which brings up the 12V rail. At time t
9
, the 12V rail
has exceeded the POR threshold and the ISL6537 enters a
reset mode that lasts for 3 soft-start cycles. At time t
10
, the 3
soft-start cycle reset is ended and the individual regulators
are enabled and soft-started in the same sequence as the
mechanical cold start sequence, with the exception that the
V
DDQ
regulator is already enabled and in regulation.
Active to Shutdown (S0 to S5 Transition)
When the system transitions from active, S0, state to
shutdown, S4/S5, state, the ISL6537 IC disables all
regulators and forces the VIDPGD pin LOW. This transition
is represented on Figure 1 at time t
15
.
Fault Protection
The ISL6537 monitors the V
DDQ
regulator for under and
overvoltage events. The V
DDQ
regulator also has overcurrent
protection. The internal V
TT_DDR
LDO regulator is monitored
for under and overvoltage events. All other regulators are
monitored for undervoltage events.
An overvoltage event on either the V
DDQ
or V
TT_DDR
regulator will cause an immediate shutdown of all regulators.
This can only be cleared by toggling the SLP_S5 signal such
that the system enters the S5 sleep state and then
transitions back to the active, S0, state.
If a regulator experiences any other fault condition (an
undervoltage or an overcurrent on V
DDQ
), then that
regulator, and only that regulator, will be disabled and an
internal fault counter will be incremented by 1. If the disabled
regulator is used as the input for another regulator, then that
cascoded regulator will also experience a fault condition due
to a loss of input. The cascoded regulator will be disabled
and the fault counter incremented by 1.
At every fault occurrence, the internal fault counter is
incremented by 1 and an internal Fault Reset Counter is
cleared to zero. The Fault Reset Counter will increment once
for every clock cycle (1 clock cycle is typically 1/250kHz, or
4μs). If the Fault Reset Counter reaches a count of 16384
before another fault occurs, then the Fault Counter is
cleared to 0. If a fault occurs prior to the Fault Reset Counter
reaching a count of 16384, then the Fault Reset Counter is
set back to zero.
The ISL6537 will immediately shut down when the Fault
Counter reaches a count of 4 when the system is restarting
from an S5 state into the active, or S0, state. The ISL6537
ISL6537
