LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
2 Rev F 7/8/15
85310I-11 DATA SHEET
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1V
CC
Power Positive supply pin.
2 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
3 CLK0 Input Pulldown Non-inverting differential clock input.
4 nCLK0 Input Pullup Inverting differential clock input.
5 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
6 CLK1 Input Pulldown Non-inverting differential clock input.
7 nCLK1 Input Pullup Inverting differential clock input.
8V
EE
Power Negative supply pin.
9, 16, 25, 32 V
CCO
Power Output supply pins.
10, 11 nQ9, Q9 Output Differential output pair. LVPECL interface levels.
12, 13 nQ8, Q8 Output Differential output pair. LVPECL interface levels.
14, 15 nQ7, Q7 Output Differential output pair. LVPECL interface levels.
17, 18 nQ6, Q6 Output Differential output pair. LVPECL interface levels.
19, 20 nQ5, Q5 Output Differential output pair. LVPECL interface levels.
21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels.
23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels.
26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface levels.
28, 29 nQ1, Q1 Output Differential output pair. LVPECL interface levels.
30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
