LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
4 Rev F 7/8/15
85310I-11 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Table 4C. DC Characteristics, V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
Item Rating
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Positive Supply Voltage 2.375 3.3 3.8 V
V
CCO
Output Supply Voltage 2.375 3.3 3.8 V
I
EE
Power Supply Current 120 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
CC
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current
CLK_EN V
CC
= V
IN
= 3.8V 5 µA
CLK_SEL V
CC
= V
IN
= 3.8V 150 µA
I
IL
Input Low Current
CLK_EN V
CC
= 3.8V, V
IN
= 0V -150 µA
CLK_SEL V
CC
= 3.8V, V
IN
= 0V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK[0:1], V
CC
= V
IN
= 3.8V 150 µA
nCLK[0:1] V
CC
= V
IN
= 3.8V 5 µA
I
IL
Input Low Current
CLK[0:1] V
CC
= 3.8V, V
IN
= 0V -5 µA
nCLK[0:1] V
CC
= 3.8V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V
V
CMR
Common Mode Range; NOTE 1, 2 V
EE
+ 0.5 V
CC
– 0.85 V
Rev F 7/8/15 5 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
85310I-11 DATA SHEET
Table 4D. LVPECL DC Characteristics, V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
CCO
– 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 500MHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CCO
– 1.4 V
CCO
– 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CCO
– 2.0 V
CCO
– 1.7 V
V
swing
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 700 MHz
t
PD
Propagation Delay; NOTE 1 2 2.5 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 140 340 ps
tsk(o) Output Skew; NOTE 3, 4 30 55 ps
tjit
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter section
<0.13 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 700 ps
odc Output Duty Cycle 47 53 %
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
6 Rev F 7/8/15
85310I-11 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)

85310AYI-11LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 10 LVPECL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet