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8714004DKILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
ICS8714004DKI REVISION A MARCH 24, 2014 4 ©2014 Integrated Device Technology, Inc.
ICS8714004I Data Sheet FemtoCLock
®
Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
17 QDIV0 Input Pulldown
Output Divider Control for Q0, nQ0. Refer to Table 3F. LVCMOS/LVTTL interface
levels.
18 QDIV1 Input Pulldown
Output Divider Control for Q1, nQ1. Refer to Table 3F. LVCMOS/LVTTL interface
levels.
19 QDIV2 Input Pulldown
Output Divider Control for Q2, nQ2. Refer to Table 3F. LVCMOS/LVTTL interface
levels.
20 QDIV3 Input Pulldown
Output Divider Control for Q3, nQ3. Refer to Table 3F. LVCMOS/LVTTL interface
levels.
21 IREF Input
An external fixed precision resistor from this pin to ground is needed to provide a
reference current for the differential HCSL outputs. A resistor value of 475:
provides an HCSL voltage swing of approximately 700mV.
23, 24
nFBOUT,
FBOUT
Output
Differential feedback output pair. The feedback output pair always switches
independent of the output enable settings on the OE[1:0] pins.
HCSL interface levels.
25, 26 nQ3, Q3 Output Differential output pair. HCSL interface levels.
28, 29 nQ2, Q2 Output Differential output pair. HCSL interface levels.
31, 32 nQ1, Q1 Output Differential output pair. HCSL interface levels.
33, 34 nQ0, Q0 Output Differential output pair. HCSL interface levels.
36 V
DDA
Power Analog supply pin.
37 CLK Input Pulldown
Non-inverting differential clock input.
Accepts HCSL, LVDS, M-LVDS, HSTL, LVPECL input levels.
38 nCLK Input
Pullup/
Pulldown
Inverting differential clock input.
Accepts HCSL, LVDS, M-LVDS, HSTL, LVPECL input levels.
39 PDIV0 Input Pulldown
Input Divide Select 0. Together with PDIV1 determines the input divider value.
Refer to Table 3E. LVCMOS/LVTTL Interface levels.
40 PDIV1 Input Pulldown
Input Divide Select 1. Together with PDIV0 determines the input divider value.
Refer to Table 3E. LVCMOS/LVTTL Interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLUP
Input Pullup Resistor 51 k:
R
PULLDOWN
Input Pulldown Resistor 51 k:
Number Name Type Description
ICS8714004DKI REVISION A MARCH 24, 2014 5 ©2014 Integrated Device Technology, Inc.
ICS8714004I Data Sheet FemtoCLock
®
Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
Function Tables
Table 3A. Common Configuration Table
NOTE 1
NOTE 1: This table shows common configurations and is not exhaustive. When using alternate configurations, the user must ensure the VCO
frequency is always within its range of 490MHz – 660MHz.
Table 3B. Output Enable Truth Table
Table 3C. Feedback Input Divider Control Table
Table 3D. Feedback Output Divider Control Table
Table 3E. Input Divide Select Control Table
Table 3F. Output Divider Control Control Table
Input
Frequency
Output
Frequency Application
Frequency
Mult. Factor PDIV FBI_DIV FBO_DIV QDIVx
100MHz 100MHz PCIe Buffer 1 ÷1 ÷1 ÷5 ÷5
125MHz 125MHz PCIe, Ethernet Buffer 1 ÷1 ÷1 ÷4 ÷4
100MHz 125MHz PCIe Multiplier 5/4 ÷1 ÷1 ÷5 ÷4
125MHz 100MHz PCIe Divider 4/5 ÷1 ÷1 ÷4 ÷5
25MHz 100MHz PCIe Multiplier 4 ÷1 ÷4 ÷5 ÷5
25MHz 125MHz PCIe, Ethernet Multiplier 5 ÷1 ÷4 ÷5 ÷4
25MHz 156.25MHz XAUI Multiplier 25/4 ÷1 ÷5 ÷5 ÷4
62.5MHz 125MHz Ethernet Multiplier 2 ÷1 ÷2 ÷4 ÷4
53.125MHz 106.25MHz Fibre Channel Multiplier 2 ÷1 ÷2 ÷5 ÷5
Inputs Output State
OE1 OE0 Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3
0 0 Q0, nQ0 switching
Disabled
(High Impedance)
Disabled
(High Impedance)
Disabled
(High Impedance)
0 1 Q0, nQ0 switching Q1, nQ1 switching
Disabled
(High Impedance)
Disabled
(High Impedance)
1 0 Q0, nQ0 switching Q1, nQ1 switching Q2, nQ2 switching
Disabled
(High Impedance)
1(default) 1(default) Q0, nQ0 switching Q1, nQ1 switching Q2, nQ2 switching Q3, nQ3 switching
Inputs
Feedback Input Divider ValuesFBI_DIV1 FBI_DIV0
00 ÷1
01 ÷2
10 ÷4
1 1 ÷5 (default)
Inputs
Feedback Output Divider ValueFBO_DIV
0 ÷4 (default)
1÷5
Inputs
Input Divider ValuesPDIV1 PDIV0
0 0 ÷4 (default)
01 ÷5
10 ÷8
11 ÷1
Inputs
Output Divider ValueQDIV[3:0]
0 ÷4 (default)
1÷5
ICS8714004DKI REVISION A MARCH 24, 2014 6 ©2014 Integrated Device Technology, Inc.
ICS8714004I Data Sheet FemtoCLock
®
Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance, T
JA
32.4qC/W (0 mps)
Storage Temperature, T
STG
-65qC to 150qC
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage V
DD
– 0.15 3.3 V
DD
V
I
DD
Power Supply Current Outputs Unloaded 170 210 mA
I
DDA
Analog Supply Current Outputs Unloaded 11 15 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2.2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input
High Current
MR, PDIV[1:0],
QDIV[3:0], FBO_DIV
V
DD
= V
IN
= 3.465V 150 μA
PLL_SEL, OE_MLVDS,
FBI_DIV[1:0], OE[1:0]
V
DD
= V
IN
= 3.465V 5 μA
I
IL
Input
Low Current
MR, PDIV[1:0],
QDIV[3:0], FBO_DIV
V
DD
= 3.465V, V
IN
= 0V -5 μA
PLL_SEL, OE_MLVDS,
FBI_DIV[1:0], OE[1:0]
V
DD
= 3.465V, V
IN
= 0V -150 μA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

8714004DKILFT

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Description:
Clock Buffer FemtoClock Zero Delay Buffer PCIe
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