ICS8714004DKI REVISION A MARCH 24, 2014 9 ©2014 Integrated Device Technology, Inc.
ICS8714004I Data Sheet FemtoCLock
®
Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
Table 5B. AC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. Characterized with configurations in Table 3A.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Refer to the Phase Noise plots.
NOTE 4: Measurements depend on input source used.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measurement taken from a differential waveform.
NOTE 9: t
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100mV differential range. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
See Parameter Measurement Information Section.
NOTE 14: Input duty cycle must be 50%.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 98 165 MHz
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 35 80 ps
tsk(o) Output Skew; NOTE 1, 2 Outputs measured Q[0:3] 100 210 ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3, 4
125MHz, Integration Range:
1.875MHz – 20MHz
0.558 ps
100MHz, Integration Range:
1.875MHz – 20MHz
0.567 ps
t
L
PLL Lock Time 100 ms
V
MAX
Absolute Max Output Voltage;
NOTE 5, 6
1150 mV
V
MIN
Absolute Min Output Voltage;
NOTE 5, 7
-300 mV
V
RB
Ringback Voltage; NOTE 8, 9 -100 100 mV
t
STABLE
Time before V
RB
is allowed;
NOTE 8, 9
500 ps
V
CROSS
Absolute Crossing Voltage;
NOTE 10, 11
150 550 mV
'V
CROSS
Total Variation of V
CROSS
over
all edges; NOTE 10, 12
140 mV
Rise/Fall Edge Rate
Rising/Falling Edge Rate;
NOTE 8, 13
Measured between
-150mV to +150mV
0.6 4 V/ns
odc Output Duty Cycle; NOTE 14 45 55 %
