15
1994fb
LT1994
In general, the die temperature can be estimated from
the ambient temperature T
A
, and the device power dis-
sipation P
D
:
T
J
= T
A
+
+ P
D
• θ
JA
The power dissipation in the IC is a function of the supply
voltage, the output voltage, and the load resistance. For
fully differential output amplifi ers at a given supply voltage
(±V
CC
), and a given differential load (R
LOAD
), the worst-
case power dissipation P
D(MAX)
occurs at the worst-case
quiescent current (I
Q(MAX)
= 20.5mA) and when the load
current is given by the expression:
I
V
R
LOAD
CC
LOAD
=
The worst-case power dissipation in the LT1994 at
I
V
R
LOAD
CC
LOAD
=
is:
PVIII
R
V
R
VI
DMAX
CC LOAD
Q MAX
LOAD
LOAD
CC
LOAD
CC
QMAX
() ()
()
=+
()
=+
2
2
2
2
•• – •
••
Example: A LT1994 is mounted on a circuit board in a
MSOP-8 package (θ
JA
= 140°C/W), and is running off of
±5V supplies driving an equivalent load (external load plus
feedback network) of 75Ω. The worst-case power that
would be dissipated in the device occurs when:
P
V
R
VI
V
V
DMAX
CC
LOAD
CC
QMAX
() ()
=+
=+
2
2
2
5
75
25
••
•
Ω
••. .17 5 0 54MA W=
The maximum ambient temperature the 8-lead MSOP is
allowed to operate under these conditions is:
T
A
= T
JMAX
– P
D
• θ
JA
= 150°C – (0.54W) •
(140°C/W) = 75°C
To operate the device at higher ambient temperature,
connect more copper to the V
–
pin to reduce the thermal
resistance of the package as indicated in Table 1.
Table 1. LT1994 MSOP Package Thermal Resistivity
COPPER AREA
TOPSIDE (mm
2
)
COPPER AREA
BACKSIDE (mm
2
)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
00 140
30 0 135
100 0 130
100 100 120
540 540 110
Layout Considerations
Because the LT1994 is a high speed amplifi er, it is sensitive
to both stray capacitance and stray inductance. Compo-
nents connected to the LT1994 should be connected with
as short and direct connections as possible. A low noise,
low impedance ground plane is critical for the highest
performance. In single-supply applications, high quality
surface mount 1F and 0.1F ceramic bypass capacitors
with minimum PCB trace should be used directly across
the power supplies V
+
to V
–
. In split supply applications,
high quality surface mount 1F and 0.1F ceramic bypass
capacitors should be placed across the power supplies
V
+
to V
–
, and individual high quality surface mount 0.1F
bypass capacitors should be used from each supply to
ground with direct (short) connections.
Any stray parasitic capacitance to ground at the summing
junctions, IN
+
and IN
–
should be kept to an absolute mini-
mum even if it means stripping back the ground plane
away from any trace attached to this node. This becomes
especially true when the feedback resistor network uses
resistor values >500Ω in circuits with R
F
= R
I
. Excessive
peaking in the frequency response can be mitigated by
adding small amounts of feedback capacitance around RF
(2pF to 5pF). Always keep in mind the differential nature of
the LT1994, and that it is critical that the output impedances
seen by both outputs (stray or intended) should be as bal-
anced and symmetric as possible. This will help preserve
the natural balance of the LT1994, which minimizes the
generation of even order harmonics, and preserves the
rejection of common mode signals and noise.
It is highly recommended that the V
OCM
pin be either hard
tied to a low impedance ground plane (in split supply
applications) or bypassed to ground with a high quality
APPLICATIONS INFORMATION
