9
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LT1994
IN
+
, IN
–
(Pins 1, 8): Noninverting and Inverting Input
Pins of the Amplifi er, Respectively. For best performance,
it is highly recommended that stray capacitance be
kept to an absolute minimum by keeping printed circuit
connections as short as possible, and if necessary, strip-
ping back nearby surrounding ground plane away from
these pins.
V
OCM
(Pin 2): Output Common Mode Reference Voltage.
The V
OCM
pin is the midpoint of an internal resistive volt-
age divider between the supplies, developing a (default)
mid-supply voltage potential to maximize output signal
swing. V
OCM
has a Thevenin equivalent resistance of
approximately 40k and can be overdriven by an external
voltage reference. The voltage on V
OCM
sets the output
common mode voltage level (which is defi ned as the av-
erage of the voltages on the OUT
+
and OUT
–
pins). V
OCM
should be bypassed with a high quality ceramic bypass
capacitor of at least 0.1F (unless connected directly to
a low impedance, low noise ground plane) to minimize
common mode noise from being converted to differen-
tial noise by impedance mismatches both externally and
internally to the IC.
V
+
, V
–
(Pins 3, 6): Power Supply Pins. For single-supply
applications (Pin 6 grounded) it is recommended that
high quality 1F and 0.1µF ceramic bypass capacitors be
placed from the positive supply pin (Pin 3) to the negative
supply pin (Pin 6) with minimal routing. Pin 6 should be
directly tied to a low impedance ground plane. For dual
power supplies, it is recommended that high quality, 0.1F
ceramic capacitors are used to bypass Pin 3 to ground
and Pin 6 to ground. It is also highly recommended that
high quality 1µF and 0.1µF ceramic bypass capacitors be
placed across the power supply pins (Pins 3 and 6) with
minimal routing.
OUT
+
, OUT
–
(Pins 4, 5): Output Pins. Each pin can drive
approximately 100Ω to ground with a short-circuit current
limit of up to ±85mA. Each amplifi er output is designed
to drive a load capacitance of 25pF. This basically means
the amplifi er can drive 25pF from each output to ground
or 12.5pF differentially. Larger capacitive loads should be
decoupled with at least 25Ω resistors from each output.
SHDN (Pin 7): When Pin 7 (SHDN) is fl oating or when
Pin 7 is directly tied to V
+
, the LT1994 is in the normal
operating mode. When Pin 7 is pulled a minimum of 2.1V
below V
+
, the LT1994 enters into a low power shutdown
state. Refer to the SHDN pin section under Applications
Information for a description of the LT1994 output imped-
ance in the shutdown state.
PIN FUNCTIONS
