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932S890CKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT®
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 10
932S890C REV D 052011
Electrical Characteristics–USB - 48MHz, SIO 48/24MHz
Electrical Characteristics–REF-14.318MHz
PARAMETER S YMBOL CONDITIO NS* MIN TYP MAX UNITS NOTES
Long Accuracy ppm see Tperiod min-max values -50 +50 ppm 1,2
Clock period T
PERIOD
US B output nominal 20.702 20.833 20.964 ns 3,5
Clock Low Time
T
LOW
Measure from < 0.6V 9.375 11.458 ns 3
Clock H igh Time
T
HIGH
Measure from > 2.0V 9.375 11.458 ns 3
Ris e Tim e t
r_US B
V
OL
= 20% of Voh,
V
OH
= 80%of Voh
0.5 3 ns
1
Fall Tim e
t
f_USB
V
OL
= 20% of Voh,
V
OH
= 80%of Voh
0.5 3 ns
1
Output High Voltage V
OH USB
I
OH
= -1 mA 2.4 V 1,3
Output Low Voltage V
OLUSB
I
OL
= 1 mA 0.4 V 1,3
Output High Voltage
V
OH S I O
I
OH
= -0.2 mA
1.8 2 2.2 V 1,4
Output Low Voltage
V
OLSIO
I
OL
= 0.2 mA
0.4 V 1,4
Duty Cycle
d
C YCUSB
V
T
= 1.5 V 45 55
%1,3
Skew t
SKEW
V
T
= 1.5 V 250 ps 1
Jitter, Cycle to cycle t
jCYC-C YC
V
T
= 1.5 V 130 ps 1,3
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by desig n and characterization, not 100% tested in production.
2
IDT recommended and/or chipset vendor layout guidelines mu st be follo wed to meet this specification
3
Applies to USB outputs only
4
Applies to SIO outputs only
5
SIO 24MHz outputs are 1/2 of USB48MHz frequency (twice the period). Includes cycle to cycle jitter.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values -50 +50 ppm 1,2
Long Term Jitter t
jLT
@ 1us 500 ps 1,2
Clock period
T
PERIOD
14.318MHz output nominal 69.6378 69.8413 70.0448 ns 2,3
Clock Low Time
T
LOW
Measure from V
T
= 50%
2ns2
Clock H igh Time T
HIGH
Measure from V
T
= 50% 2 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 2.8 3.3 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0 0.4 V 1
Ris e T ime t
R
V
OL
= 20% of V
OH
,
V
OH
= 80%of V
OH
1.5 ns 1
Fall Time t
F
V
OL
= 20% of V
OH
,
V
OH
= 80%of V
OH
1.5 ns 1
Skew t
SKEW
Measure from V
T
= 50% 250 ps 1
Duty Cycle d
t1
V
T
= V
OH
/2 45 55 % 1
Jitter, Cycle to Cycle
t
jCYC-C YC
Measure from V
T
= 50%
200 ps 1
Jitter, Peak to Peak t
jPK-PK
Measure from V
T
= 50% (0.9V)
t
jpk-pk
=[|t
jcy c-cyc
max| + |t
jcyc -cyc
min|]/2
200 ps 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by desig n and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
Includes cycle to cycle jitter.
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT®
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 11
932S890C REV D 052011
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Clock Periods–Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0pp m + pp m error +SSC Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long -Term
Average
Short-term
Average
Period
Mini mu m
Absolute
Period
Minimum
Absol ute
Period
Minimum
Absol ute
Period
No minal M axim um Maxi mum Maximu m
HTT/SRC 100
9.87456 9.99956 10.02456 10.02506 10.02556 10.05056 10.17556 ns 1,2
CPU 200
4.84978 4.99978 5.01228 5.01253 5.01278 5.02528 5.17528 ns 1,2
Notes
Symbol
Definition
Signal Name
Measurement Window
Units
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0pp m + pp m error +SSC Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long -Term
Average
Short-term
Average
Period
Mini mu m
Absolute
Period
Minimum
Absol ute
Period
Minimum
Absol ute
Period
No minal M axim um Maxi mum Maximu m
SRC 100
9.87450 9.99950 10.00000 10.00050 10.12550 ns 1,2
SATA 100
9.87450 9.99950 10.00000 10.00050 10.12550 ns 1,2
CPU 200
4.84975 4.99975 5.00000 5.00025 5.15025 ns 1,2
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
All Lon
g
Term Accurac
y
and Clock Period s
p
ecifications are
g
uaranteed assumin
g
that REFOUT is at 14.31818MHz
Signal Name
Notes
Symbol
Definition
Units
Measurement Window
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT®
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 12
932S890C REV D 052011
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Read Address Write Address
D3
(H)
D2
(H)
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

932S890CKLF

Mfr. #:
Buy 932S890CKLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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