932S890CKLF Datasheet 932S890CKLF, 932S890CKLFT | P13-P15

932S890C

RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS

IDT®

RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 13

932S890C REV D 052011

SMBus Table: Output Enable Control Register

Byte 0 Name Description Type 0 1 Default

Bit 7

HTT1_OE Output Enable RW Low/Low Enabled 1

Bit 6

HTT0_OE Output Enable RW Low/Low Enabled 1

Bit 5

REF0_ OE Output Enable RW Low Enabled 1

Bit 4

REF1_ OE Output Enable RW Low Enabled 1

Bit 3

SIO_0_OE Out

ut Enable R

Hi-Z

Enabled 1

Bit 2

SIO_1_OE Out

ut Enable R

Low Enabled 1

Bit 1

48MHz_1_OE Out

ut Enable R

Low Enabled 1

Bit 0

48MHz_0_OE Outp ut Enable RW Low Enabled 1

SMBus Table:Output Enable Control Register

Byte 1 Name Control Function Type 0 1 Default

Bit 7

SRC13_OE Output Enable RW Low/Low Enabled 1

Bit 6

SRC12_OE Output Enable RW Low/Low Enabled 1

Bit 5

SRC11_OE Output Enable RW Low/Low Enabled 1

Bit 4

SRC10_OE Output Enable RW Low/Low Enabled 1

Bit 3

SRC9_OE Output Enable RW Low/Low Enabled 1

Bit 2

SRC8_OE Output Enable RW Low/Low Enabled 1

Bit 1

SRC7_OE Output Enable RW Low/Low Enabled 1

Bit 0

SRC6_OE Output Enable RW Low/Low Enabled 1

SMBus Table: Output Enable Control Re

iste

Byte 2 Name Control Function Type 0 1 Default

Bit 7

SRC5_OE Output Enable RW Low/Low Enabled 1

Bit 6

SRC4_OE Output Enable RW Low/Low Enabled 1

Bit 5

SRC3_OE Output Enable RW Low/Low Enabled 1

Bit 4

SRC2_OE Output Enable RW Low/Low Enabled 1

Bit 3

SRC1_OE Output Enable RW Low/Low Enabled 1

Bit 2

SRC0_OE Output Enable RW Low/Low Enabled 1

Bit 1

SATA_OE Output Enable RW Low/Low Enabled 1

Bit 0

CPU0_OE Output Enable RW Low/Low Enabled 1

SMBus Table: CPU/HTT Frequency and Output Enable Control Re

iste

Byte 3 Name Control Function Type 0 1 Default

Bit 7

CPU3_OE Output enable RW Low/Low Enabled 1

Bit 6

CPU2_OE Output enable RW Low/Low Enabled 1

Bit 5

CPU1_OE Output enable RW Low/Low Enabled 1

Bit 4

CPU SS Enable Spread Enable RW SS Off SS On 0

Bit 3

CPU Spread Type Down or Center Spread RW 0.5% Down Spread

0.5% Cente r Spread

(

+/-0. 25%

)

Bit 2

CPU_FS2 CPU Frequency Select RW 1

Bit 1

CPU_FS1 CPU Frequency Select RW 0

Bit 0

CPU_FS0 CPU Frequency Select LSB RW 0

SMBus Table: SRC Frequency Control Re

ister

Byte 4 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

SRC SS Enable

read Enable R

SS Of f SS On 0

Bit 3

SRC S

read T

e Down or Center S

re ad R

0.5% Down S

re ad 0.5% Center S

Bit 2

SRC_FS2 SRC Fre

uenc

Select R

Bit 1

SRC_FS1 SRC Fre

uenc

Select R

Bit 0

SRC_FS0 SRC Frequency Select LSB RW 0

Reserved

See CPU Frequency Select Table

Default value corresponds to 200MHz.

Note that HTT frequency tracks the CPU frequency

and is equal to 1/2 for CPU.

See SRC Freque ncy Select Table

Default Corresponds to 100MHz

932S890C

RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS

IDT®

RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 14

932S890C REV D 052011

SMBus Table: N-Step Select and SIO Readback Register

Byte 5 Name Control Function Type 0 1 Default

Bit 7

SIO_ SEL Selects 24MHz or 48 MHz

24MHz 48MHz Latch

Bit 6

CPU M/N En CPU PLL M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled 0

Bit 5

SRC M/N En SRC M/N Prog.Enable R W M/N Prog. Disabled M/N Prog. Enabled 0

Bit 4

Test_Sel Selects Test Mode

Normal mode All ouputs are REF/N 0

Bit 3

Bit 2

IO_VOUT2

IO Output Voltage Select

(

Most Si

nificant Bit

)

RW 1

Bit 1

IO_VOUT1 IO Out

ut Volta

e Select R

Bit 0

IO_VOUT0

IO Output Voltage Select

(Least Significant Bit)

RW 1

SMBus Table: Byte Count Register

Byte 6 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

BC5 B

te Count bit 5

(

MSB

)

Bit 4

BC4 Byte Count bit 4 RW 0

Bit 3

BC3 Byte Count bit 3 RW 1

Bit 2

BC2 Byte Count bit 2 RW 0

Bit 1

BC1 Byte Count bit 1 RW 0

Bit 0

BC0 Byte Count bit 0 (LSB) R W 0

SMBus Table: Device ID re

ister

Byte 7 Name Control Function Type 0 1 Default

Bit 7

Device ID7

Bit 6

Device ID6

Bit 5

Device ID5

Bit 4

Device ID4

Bit 3

Device ID3

Bit 2

Device ID2

Bit 1

Device ID1

Bit 0

Device ID0

SMBus Table: Vendor & Revision ID Re

iste

Byte 8 Name Control Function Type 0 1 Default

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID 3

--0

Bit 2

VID 2

--0

Bit 1

VID 1

--0

Bit 0

VID 0

--1

SMBus Table: WatchDog Timer Control Registe

Byte 9 Name Control Function Type 0 1 Default

Bit 7

HWD_EN Watchdog Hard Alarm Enable RW

Disable and Reload Hartd

Alarm Timer, Clear WD

Hard status bit.

Enable Timer 0

Bit 6

SWD_EN Watchdog Soft Alarm Enable R W Disable Enable 0

Bit 5

WD Hard Status WD Hard Alarm Status R Normal Alarm X

Bit 4

WD Soft Status WD Soft Alarm Status R Normal Alarm X

Bit 3

WDTC trl

Watch Do g Alarm Time base

Control

RW 290ms Base 1160ms Base 0

Bit 2

HWD2 WD Hard Alarm Timer Bit 2 RW 1

Bit 1

HWD1 WD Hard Alarm Timer Bit 1 RW 1

Bit 0

HWD0 WD Hard Alarm Timer Bit 0 RW 1

Rev A = 0000

Rev B = 0001

Rev C = 0010

These bits represent the number of Watch Dog Time

Base Units that pass b efore the Watch Alarm expires.

Default is 7 X 290ms = 2s.

VENDOR ID

REVISION ID

Device ID 89 hex for 932S820

Determines the number of bytes that are read b ack

from the device. Default is 08 hex.

Reserved

See Table 2: V_IO Selection

(Default is 0.8V)

932S890C

RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS

IDT®

RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 15

932S890C REV D 052011

SMBus Table: WD Timer Safe Frequency Control Register

Byte 10 Name Control Function Type 0 1 Default

Bit 7

SWD2 WD Soft Alarm Timer Bit 2 RW 1

Bit 6

SWD1 WD Soft Alarm Timer Bit 1 RW 1

Bit 5

SWD0 WD Soft Alarm Timer Bit 0 RW 1

Bit 4

WD SF4 RW 0

Bit 3

WD SF3 RW 0

Bit 2

WD SF2 RW 1

Bit 1

WD SF1 RW 0

Bit 0

WD SF0 RW 0

SMBus Table: CPU PLL Frequency Control Register

Byte 11 Name Control Function Type 0 1 Default

Bit 7

N Div2 N Divider Prog bit 2 RW X

Bit 6

N Div1 N Divider Prog bit 1 RW X

Bit 5

M Div5 RW X

Bit 4

M Div4 RW X

Bit 3

M Div3 RW X

Bit 2

M Div2 RW X

Bit 1

M Div1 RW X

Bit 0

M Div0 RW X

SMBus Table: CPU PLL Frequency Control Re

ister

Byte 12 Name Control Function Type 0 1 Default

Bit 7

N Div10 RW X

Bit 6

N Div9 RW X

Bit 5

N Div8 RW X

Bit 4

N Div7 RW X

Bit 3

N Div6 RW X

Bit 2

N Div5 RW X

Bit 1

N Div4 RW X

Bit 0

N Div3 RW X

SMBus Table: CPU PLL Spread Spectrum Control Re

ister

Byte 13 Name Control Function Type 0 1 Default

Bit 7

SSP7 R W X

Bit 6

SSP6 R W X

Bit 5

SSP5 R W X

Bit 4

SSP4 R W X

Bit 3

SSP3 R W X

Bit 2

SSP2 R W X

Bit 1

SSP1 R W X

Bit 0

SSP0 R W X

SMBus Table: CPU PLL Spread Spectrum Control Re

ister

Byte 14 Name Control Function Type 0 1 Default

Bit 7

SSP15 R W X

Bit 6

SSP14 R W X

Bit 5

SSP13 R W X

Bit 4

SSP12 R W X

Bit 3

SSP11 R W X

Bit 2

SSP10 R W X

Bit 1

SSP9 R W X

Bit 0

SSP8 R W X

Watch Dog Hard Alarm Safe

Freq Programming bits

These bits represent the number of Watch Dog Time

Base Units that pass before the Watch Alarm expires.

Default is 7 X 290ms = 2s.

These bits configure the safe frequency that the device

returns to if the Watchdog Hardware Timer expires.

The value show here corresponds to the power up

default of the device. See the various Frequency Select

Tables for the exact frequencies.

The decimal representation of M and N Divider in Byte

16 and 17 will configure the VCO frequency. Default at

power up = Byte 3 Rom table. See M/N Caculation

Tables for VCO fre quency formulas.

Note: If CLKREQA and CLKREQB are both selected to control an output, the control condition is an OR function. CLKREQA# = 0

OR CLKREQB = 0 results in the controlled output running.

Spread Spectrum

Programming b(15:8)

These bits set the CPU spread pecentage.Please

contact IDT for the appropriate values.

Spread Spectrum

Programming b(7:0)

These bits set the CPU spread pecentage.Please

contact IDT for the appropriate values.

M Divider Programming bits

The decimal representation of M and N Divider in Byte

16 and 17 will configure the VCO frequency. Default at

power up = Byte 3 Rom table. See M/N Caculation

Tables for VCO fre quency formulas.

N Divider Programming

b(10:3)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

932S890CKLF

Mfr. #:

Buy 932S890CKLF

Manufacturer:

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Description:

Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK

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932S890CKLF

932S890CKLF

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