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MAX9205EAI+T

P1-P3P4-P6P7-P9P10-P12P13-P13
19-2029; Rev 2; 10/12
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
EVALUATION KIT AVAILABLE
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
General Description
The MAX9205/MAX9207 serializers transform 10-bit-
wide parallel LVCMOS/LVTTL data into a serial high-
speed bus low-voltage differential signaling (LVDS)
data stream. The serializers typically pair with deserial-
izers like the MAX9206/MAX9208, which receive the
serial output and transform it back to 10-bit-wide paral-
lel data.
The MAX9205/MAX9207 transmit serial data at speeds
up to 400Mbps and 660Mbps, respectively, over PCB
traces or twisted-pair cables. Since the clock is recov-
ered from the serial data stream, clock-to-data and
data-to-data skew that would be present with a parallel
bus are eliminated.
The serializers require no external components and few
control signals. The input data strobe edge is selected
by TCLK_R/F. PWRDN is used to save power when the
devices are not in use. Upon power-up, a synchroniza-
tion mode is activated, which is controlled by two SYNC
inputs, SYNC1 and SYNC2.
The MAX9205 can lock to a 16MHz to 40MHz system
clock, while the MAX9207 can lock to a 40MHz to
66MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock, or when the device is in power-
down mode.
Both the devices operate from a single +3.3V supply,
are specified for operation from -40°C to +85°C, and
are available in 28-pin SSOP packages.
Applications
Features
o Standalone Serializer (vs. SERDES) Ideal for
Unidirectional Links
o Framing Bits for Deserializer Resync Allow Hot
Insertion Without System Interruption
o LVDS Serial Output Rated for Point-to-Point and
Bus Applications
o Wide Reference Clock Input Range
16MHz to 40MHz (MAX9205)
40MHz to 66MHz (MAX9207)
o Low 140ps (pk-pk) Deterministic Jitter (MAX9207)
o Low 34mA Supply Current (MAX9205)
o 10-Bit Parallel LVCMOS/LVTTL Interface
o Up to 660Mbps Payload Data Rate (MAX9207)
o Programmable Active Edge on Input Latch
o Pin-Compatible Upgrades to DS92LV1021 and
DS92LV1023
PCB OR
TWISTED PAIR
TCLK
PLL
PLL
EN
EN
PWRDN
INPUT LATCH
PARALLEL-TO-SERIAL
OUTPUT LATCH
SERIAL-TO-PARALLEL
TIMING AND
CONTROL
TIMING AND
CONTROL
CLOCK
RECOVERY
RCLK
LOCK
SYNC 1
SYNC 2
OUT+
OUT-
IN+
IN-
100Ω 100Ω
TCLK_R/F
RCLK_R/F
REFCLK
OUT_
IN_
10
10
BUS
LVDS
MAX9205
MAX9207
MAX9206
MAX9208
Ordering Information
PART
TEMP
RANGE
PIN-
PACKAGE
REF CLOCK
RANGE
(MHz)
MAX9205EAI+ -40°C to +85°C 28 SSOP 16 to 40
M AX 9205E AI/V + -40°C to +85°C 28 SSOP 16 to 40
MAX9207EAI+ -40°C to +85°C 28 SSOP 40 to 66
Pin Configuration and Functional Diagram appear at end of
data sheet.
Typical Application Circuit
Cellular Phone Base
Stations
Add Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
2
Maxim Integrated
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
AVCC
= V
DVCC
= +3.0V to +3.6V, R
L
= 27Ω ±1% or 50Ω ±1%, C
L
= 10pF, T
A
= -40°C to +85°C. Typical values are at V
AVCC
=
V
DVCC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 2, 3, 4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, DVCC to GND..........................……………-0.3V to +4.0V
IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK,
PWRDN to GND......................................-0.3V to (V
CC
+ 0.3V)
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Output Short-Circuit Duration.....................................Continuous
Continuous Power Dissipation (T
A
= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, SYNC1, SYNC2, TCLK, TCLK_R/F, PWRDN)
High-Level Input Voltage V
IH
2.0 V
CC
V
Low-Level Input Voltage V
IL
GND 0.8 V
Input Current I
IN
V
IN_
= 0V or V
_VCC
-20 +20 µA
BUS LVDS OUTPUTS (OUT+, OUT-)
R
L
= 27Ω 200 286 400 mV
Differential Output Voltage V
OD
Figure 1
R
L
= 50Ω 250 460 600 mV
Change in V
OD
Between
Complementary Output States
∆V
OD
Figure 1 1 35 mV
Output Offset Voltage V
OS
Figure 1 0.9 1.15 1.3 V
Change in V
OS
Between
Complementary Output States
∆V
OS
Figure 1 3 35 mV
Output Short-Circuit Current I
OS
V
OUT+
or V
OUT-
= 0V,
IN0 to IN9 = PWRDN = EN = high
-13 -15 mA
Output High-Impedance Current I
OZ
V
PWRDN
or V
EN
= 0.8V,
V
OUT+
or V
OUT-
= 0V or V
_VCC
-10 +10 µA
Power-Off Output Current I
OX
V
_VCC
= 0V, V
OUT+
or V
OUT-
= 0V or 3.6V -10 +10 µA
POWER SUPPLY
16MHz 23 35
MAX9205
40MHz 34 45
40MHz 32 50
Supply Current I
CC
R
L
= 27_ or 50_
worst-case pattern
(Figures 2, 4)
MAX9207
66MHz 45 60
mA
Power-Down Supply Current I
CCX
PWRDN = low 8 mA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial
.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
SSOP
Junction-to-Ambient Thermal Resistance (θ
JA
)...............68°C/W
Junction-to-Case Thermal Resistance (θ
JC
)......................25°C/W
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
3
Maxim Integrated
AC ELECTRICAL CHARACTERISTICS
(V
AVCC
= V
DVCC
= +3.0V to +3.6V, R
L
= 27Ω ±1% or 50Ω ±1%, C
L
= 10pF, T
A
= -40°C to +85°C. Typical values are at V
AVCC
=
V
DVCC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 3, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS
MAX9205 16 40 MHz
TCLK Center Frequency f
TCCF
MAX9207 40 66 MHz
TCLK Frequency Variation TCFV -200 200 ppm
MAX9205 25 62.5
TCLK Period t
TCP
MAX9207 15.15 25
ns
TCLK Duty Cycle TCDC 40 60 %
TCLK Input Transition Time t
CLKT
Figure 3 3 6 ns
TCLK Input Jitter t
JIT
150
ps
(RMS)
SWITCHING CHARACTERISTICS
R
L
= 27 150 300 400
Low-to-High Transition Time t
LHT
Figure 4
R
L
= 50 150 350 500
ps
R
L
= 27 150 300 400
High-to-Low Transition Time t
HLT
Figure 4
R
L
= 50 150 350 500
ps
IN_ Setup to TCLK t
S
Figure 5 1 ns
IN_ Hold from TCLK t
H
Figure 5 3 ns
OUTPUT High State to High-
Impedance Delay
t
HZ
Figures 6, 7 4.5 10 ns
OUTPUT Low State to High-
Impedance Delay
t
LZ
Figures 6, 7 4.5 10 ns
OUTPUT High Impedance to
High-State Delay
t
ZH
Figures 6, 7 4.5 10 ns
OUTPUT High Impedance to
Low-State Delay
t
ZL
Figures 6, 7 4.5 10 ns
SYNC Pulse Width t
SPW
6 x t
TCP
ns
PLL Lock Time t
PL
Figure 7
2048 x
t
TCP
2049 x
t
TCP
ns
Bus LVDS Bit Width t
BIT
t
TCP
/12 ns
Serializer Delay t
SD
Figure 8 t
TCP
/ 6
(t
TCP
/6)
+ 5
ns
P1-P3P4-P6P7-P9P10-P12P13-P13

MAX9205EAI+T

Mfr. #:
Buy MAX9205EAI+T
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes 10-Bit Bus LVDS Serializer
Lifecycle:
New from this manufacturer.
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