MAX9205/MAX9207
10-Bit Bus LVDS Serializers
10
Maxim Integrated
Topologies
The serializers can operate in a variety of topologies.
Examples of double-terminated point-to-point, mul-
tidrop, point-to-point broadcast, and multipoint topolo-
gies are shown in Figures 11 through 14. Use 1%
surface-mount termination resistors.
A point-to-point connection terminated at each end in
the characteristic impedance of the cable or PCB
traces is shown in Figure 11. The total load seen by the
serializer is 50. The double termination typically
reduces reflections compared to a single 100 termi-
nation. A single 100 termination at the deserializer
input is feasible and will make the differential signal
swing larger.
A serializer located at one end of a backplane bus dri-
ving multiple deserializers in a multidrop configuration
is shown in Figure 12. A 54 resistor at the far end ter-
minates the bus. This topology allows “broadcast” of
data with a minimum of interconnect.
100
PARALLEL
DATA OUT
PARALLEL
DATA IN
MAX9206
MAX9208
MAX9205
MAX9207
100
SERIALIZED DATA
Figure 11. Double-Terminated Point-to-Point
54
ASIC
ASIC ASIC ASIC ASIC
MAX9205
MAX9207
MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
Figure 12. Multidrop
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
11
Maxim Integrated
100
100
ASIC
ASIC ASIC
100
100
MAX9205
MAX9207
MAX9150
REPEATER
MAX9206
MAX9208
MAX9206
MAX9208
Figure 13. Point-to-Point Broadcast Using MAX9150 Repeater
A point-to-point version of the multidrop bus is shown in
Figure 13. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to the multidrop bus, more interconnect is
traded for more robust hot-plug capability.
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter subtracts from the serial-
izer-deserializer timing margin, a low-jitter repeater is
essential in most high data rate applications.
Multiple serializers and deserializers bused over a dif-
ferential serial connection on a backplane are shown in
Figure 14. The second serializer can be a backup to
the primary serializer. The typical close spacing (1in or
less) of cards on a backplane reduces the characteris-
tic impedance by as much as half the initial, unloaded
value. Termination resistors that match the loaded char-
acteristic impedance are required at each end of the
bus. The total loaded seen by the serializer is 27 in
this case.
Board Layout
For bus LVDS applications, a four-layer PCB that pro-
vides separate power, ground, and input/output signals
is recommended. Separate LVTTL/LVCMOS and bus
LVDS signals from each other to prevent coupling into
the bus LVDS lines.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
12
Maxim Integrated
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
MAX9205
MAX9207
SYNC1
SYNC2
IN0
IN1
IN2
IN3
TCLK
IN4
IN5
IN6
IN7
IN8
IN9
TCLK_R/F
DGND
DGND
AVCC
AGND
EN
AGND
OUT-
OUT+
AGND
PWRDN
AGND
AVCC
DVCC
DVCC
+
SSOP
OUT+
OUT-
EN
10
IN_
TCLK_R/F
TCLK
SYNC 1
SYNC 2
PLL
INPUT LATCH
PARALLEL-TO-SERIAL
TIMING AND
CONTROL
PWRDN
MAX9205
MAX9207
Functional DiagramPin Configuration
54
ASIC
ASIC ASIC ASIC ASIC
54
MAX9205
MAX9207
MAX9205
MAX9207
MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
Figure 14. Multipoint
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages
. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
28 SSOP A28+4
21-0056
90-0095

MAX9205EAI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes 10-Bit Bus LVDS Serializer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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