MAX9205/MAX9207
10-Bit Bus LVDS Serializers
7
Maxim Integrated
Applications Information
Power-Supply Bypassing
Bypass AVCC with high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to AVCC. Bypass DVCC with high-fre-
quency surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smaller valued capacitor closest to DVCC.
Differential Traces and Termination
Output trace characteristics affect the performance of
the MAX9205/MAX9207. Use controlled-impedance
media and terminate at both ends of the transmission
line in the media's characteristic impedance.
Termination with a single resistor at the end of a point-
to-point link typically provides acceptable performance.
However, the MAX9205/MAX9207 output levels are
specified for double-terminated point-to-point and mul-
tipoint applications. With a single 100 termination, the
output swing is larger.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
The differential output signals should be routed close to
each other to cancel their external magnetic field.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90° turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
OUT+
OUT-
V
OD
V
OS
R
L
2
R
L
2
Figure 1. Output Voltage Definitions
TCLK
ODD IN_
EVEN IN_
TCLK_R/F = LOW
Figure 2. Worst-Case I
CC
Test Pattern
TCLK
t
CLKT
10%
90%
90%
10%
t
CLKT
0
3V
Figure 3. Input Clock Transition Time Requirement
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
8
Maxim Integrated
V
DIFF
V
DIFF
= 0
t
HLT
20%
80%
80%
20%
t
LHT
OUT+
10pF
10pF
OUT-
R
L
V
DIFF
= (OUT+) - (OUT-)
Figure 4. Output Load and Transition Times
TCLK
IN_
1.5V
1.5V1.5V
t
H
t
S
t
TCP
1.5V
TIMING SHOWN FOR TCLK_R/F = LOW
1.5V
Figure 5. Data Input Setup and Hold Times
1.5V
1.5V
t
LZ
t
HZ
t
ZL
t
ZH
3V
0
1.1V
V
OL
V
OH
OUT±
1.1V
50%50%
50%50%
EN
OUT+
OUT-
PARASITIC PACKAGE AND
TRACE CAPACITANCE
+1.1V
10pF
13.5
13.5
10pF
EN
Figure 6. High-Impedance Test Circuit and Timing
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
9
Maxim Integrated
PWRDN
TCLK
OUT±
t
PL
ACTIVE
2.0V
0.8V
1.5V
t
HZ
OR t
LZ
t
ZH
OR t
ZL
SYNC 1 = SYNC 2 = LOW
EN = HIGH
TCLK_R/F = HIGH
HIGH IMPEDANCEHIGH IMPEDANCE
Figure 7. PLL Lock Time and PWRDN High-Impedance Delays
TCLK
OUT±
IN
IN0 - IN9 SYMBOL N
IN0 - IN9 SYMBOL N + 1
t
SD
START BIT
V
DIFF
= 0 V
DIFF
= (OUT+) - (OUT-)TCLK_ R/F = HIGH
1.5V
STOP BIT START BIT STOP BIT
OUT0 - OUT9 SYMBOL N+1
OUT0 - OUT9 SYMBOL N
TIMING SHOWN FOR TCLK_R/F = HIGH
Figure 8. Serializer Delay
(OUT+) - (OUT-)
WAVEFORM
SUPERIMPOSED RANDOM DATA
O DIFFERENTIAL
t
DJIT
Figure 9. Definition of Deterministic Jitter (t
DJIT
)
(OUT+) - (OUT-)
WAVEFORM
"CLOCK" PATTERN (1010...)
t
RJIT
t
RJIT
O DIFFERENTIAL
Figure 10. Definition of Random Jitter (t
RJIT
)

MAX9205EAI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes 10-Bit Bus LVDS Serializer
Lifecycle:
New from this manufacturer.
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