FSA4480
www.onsemi.com
11
Table 6. I
2
C SPECIFICATION
(V
CC
= 2.7 V to 5.5, V
CC
(Typ.) = 3.3 V ,T
A
= −40°C to 85°C. T
A
(Typ.) = 25°C, unless otherwise specified)
Symbol
Parameter
Fast Mode
Min. Max. Unit
f
SCL
I
2
C_SCL Clock Frequency 400 kHz
t
HD;
STA
Hold Time (Repeated) START Condition 0.6
ms
t
LOW
Low Period of I
2
C_SCL Clock 1.3
ms
t
HIGH
High Period of I
2
C_SCL Clock 0.6
ms
t
SU;
STA
Set−up Time for Repeated START Condition 0.6
ms
t
HD;
DAT
Data Hold Time (Note 2) 0 0.9
ms
t
SU;
DAT
Data Set−up Time (Note 3) 100 ns
t
r
Rise Time of I
2
C_SDA and I
2
C_SCL Signals (Note 3) 20 + 0.1C
b
300 ns
t
f
Fall Time of I
2
C_SDA and I
2
C_SCL Signals (Note 3) 20 + 0.1C
b
300 ns
t
SU;
STO
Set−up Time for STOP Condition 0.6
ms
t
BUF
Bus−Free Time between STOP and START Conditions 1.3
ms
t
SP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns
2. Guaranteed by design, not production tested.
3. A fast−mode I
2
C−bus device can be used in a standard−mode I
2
C−bus system, but the requirement t
SU;DAT
≥ ±250 ns must be met. This
is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. If such a device does stretch the LOW period
of the I
2
C_SCL signal, it must output the next data bit to the I
2
C_SDA line t
r_max
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the
standard−mode I
2
C bus specification) before the I
2
C_SCL line is released.
Figure 3. Definition of Timing for Full−Speed Mode Devices on the I
2
C Bus
