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FSA4480UCX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
FSA4480
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13
Table 8. REGISTER MAPS
ADDR BIT0BIT1BIT2BIT3BIT4BIT5BIT6BIT7
Reset
Value
TypeRegister Name
0DH Timing Delay
between R
switch enable
and L switch
enable
R/W 0x00 Timing Delay between R switch enable and L switch enable control [7:0]
0EH Timing Delay
between MIC
switch enable
and L switch
enable
R/W 0x00 Timing Delay between MIC switch enable and L switch enable control [7:0]
0FH Timing Delay
between Sense
switch enable
and L switch
enable
R/W 0x00 Timing Delay between Sense switch enable and L switch enable control [7:0]
10H Timing Delay
between Audio
ground switch
enable and L
switch enable
R/W 0x00 Timing Delay between Audio ground switch enable and L switch enable control [7:0]
11H Audio accessory
status
R 0x02 Reserved CC_IN DET
12H Function enable R/W 0x08 Reserved DET I/O
Control
RES
detection
range
setting
GIPO
control
SLOW
TURN−O
N
CONTR
OLL
MIC auto
control
RES
detection
: auto
clear
Audio
jack
detection
: auto
clear
13H RES detection
pin setting
R/W 0x00 Reserved Detection pin select [2:0]
14H RES detection
value
R 0xFF R detection value [7:0]
15H
RES detection
interrupt
threshold
R/W 0x16 R detection Interrupt resistance threshold [7:0]
16H RES detection
interval
R/W 0X00 Reserved Detection interval [1:0]
17H Audio jack Status RO 0x01 Reserved 4pole,SB
U2 MIC
4pole,SB
U1 MIC
3pole No audio
18H Detection
interrupt
R/C 0x00 Reserved Audio
detection
done
RES
detection
occurred
RES
detection
done
19H Detection
interrupt Mask
R/W 0x00 Reserved Audio
detection
done
mask
RES
detection
occurred
mask
RES
detection
done
mask
1AH Audio detection
RGE1
RO 0xFF audio detection value REG1 [7:0]
1BH Audio detection
RGE2
RO 0xFF audio detection value REG2 [7:0]
1CH MIC Threshold
DATA0
R/W 0x20 MIC Threshold value DATA0 [7:0]
1DH MIC Threshold
DATA1
R/W 0xFF MIC Threshold value DATA1 [7:0]
1EH I2C Reset W/C 0x00 Reserved I2C reset
1FH Current Source
Setting
R/W 0x07 Reserved Current Source setting [3:0]
Table 9. I
2
C SLAVE ADDRESS
ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADDR = L 1 0 0 0 0 1 0 R/W
ADDR = H 1 0 0 0 0 1 1 R/W
FSA4480
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14
DEVICE ID
Address: 00h
Reset Value: 8’b 0000_1001
Type: Read
Bits
Name Size Description
7:6 Vendor ID 2 Vendor ID
5:3 Version ID 3 Device Version ID
2:0 Revision ID 3 Revision History ID
OVP INTERRUPT MASK
Address: 01h
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name Size Description
7 Reserved 1 Do Not Use
6 OVP Interrupt mask control 1 OVP Interrupt function Enable/Disable
0: Controlled by [5:0] bit
1: Mask all connector side pins OVP interrupt
5 DP_R OVP Interrupt mask control 1 0: Do not mask OVP interrupt
1: Mask OVP interrupt
4 DN_L OVP Interrupt mask control 1 0: Do not mask OVP interrupt
1: Mask OVP interrupt
3 SBU1 OVP Interrupt mask control 1 0: Do not mask OVP interrupt
1: Mask OVP interrupt
2 SBU2 OVP Interrupt mask control 1 0: Do not mask OVP interrupt
1: Mask OVP interrupt
1 GSBU1 OVP Interrupt mask control 1 0: Do not mask OVP interrupt
1: Mask OVP interrupt
0 GSBU2 OVP Interrupt mask control 1 0: Do not mask OVP interrupt
1: Mask OVP interrupt
OVP INTERRUPT FLAG
Address: 02h
Reset Value: 8’b 0000_0000
Type: Read Clear
Bits
Name Size Description
[7:6] Reserved 2 Do Not Use
5 DP_R OVP 1 0: OVP event has not occurred
1: OVP event has occurred
4 DN_L OVP 1 0: OVP event has not occurred
1: OVP event has occurred
3 SBU1 OVP 1 0: OVP event has not occurred
1: OVP event has occurred
2 SBU2 OVP 1 0: OVP event has not occurred
1: OVP event has occurred
1 GSBU1 OVP 1 0: OVP event has not occurred
1: OVP event has occurred
0 GSBU2 OVP 1 0: OVP event has not occurred
1: OVP event has occurred
FSA4480
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15
OVP STATUS
Address: 03h
Reset Value: 8’b 0000_0000
Type: Read
Bits
Name Size Description
[7:6] Reserved 2 Do Not Use
5 OVP on DP_R PIN 1 0: OVP event has not occurred
1: OVP event has occurred
4 OVP on DN_L PIN 1 0: OVP event has not occurred
1: OVP event has occurred
3 OVP on SBU1 PIN 1 0: OVP event has not occurred
1: OVP event has occurred
2 OVP on SBU2 PIN 1 0: OVP event has not occurred
1: OVP event has occurred
1 OVP on GSBU1 PIN 1 0: OVP event has not occurred
1: OVP event has occurred
0 OVP on GSBU2 PIN 1 0: OVP event has not occurred
1: OVP event has occurred
SWITCHING SETTING ENABLE
Address: 04h
Reset Value: 8’b 1001_1000
Type: Read/Write
Bits
Name Size Description
7 Device Enable 1 0: Device Disable; L, R pull down by 10 k and other switch
nodes will be high−Z for positive input.
1: Device Enable.
Device Enable = 1 Device enable = 0
ENN = 1 Device Disable Device Disable
ENN = 0 Device Enable Device Disable
6 SBU1_H to SBUx switches 1 0: Switch Disable; SBU1_H will be high−Z for positive input
1: Switch Enable
5 SBU2_H to SBUx switches 1 0: Switch Disable; SBU2_H will be high−Z for positive input
1: Switch Enable
4 DN_L to DN or L switches 1 0: Switch Disable; DN_L,DN will be high−Z for positive input. L
pull down by 10 kohm
1: Switch Enable
3 DP_R to DP or R switches 1 0: Switch Disable; DP_R,DP will be high−Z for positive input.
R pull down by 10 kohm
1: Switch Enable
2 Sense to GSBUx switches 1 0: Switch Disable; Sense,GSBU1 and GSBU2 will be high−Z for
positive input
1: Switch Enable
1 MIC to SBUx switches 1 0: Switch Disable: MIC will be high−Z for positive input.
1: Switch Enable
0 AGND to SBUx switches 1 0: Switch Disable: AGND will be high−Z for positive input.
1: Switch Enable
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

FSA4480UCX

Mfr. #:
Buy FSA4480UCX
Manufacturer:
ON Semiconductor
Description:
USB Switch ICs USB TYPE-C ANALOG SWITCH
Lifecycle:
New from this manufacturer.
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