FSA4480
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26
I
2
C INTERFACE
The FSA4480 includes a full I
2
C slave controller. The I
2
C
slave fully complies with the I
2
C specification version 2.1
requirements. This block is designed for fast mode, 400 kHz,
signals.
Examples of an I
2
C write and read sequence are shown in
below figures respectively.
Figure 6. I
2
C Write Example
SWR A A
A
A
A
A P
8bits 8bits 8bits
Write Data K+2
Slave Address Register Address K Write Data Write Data K+1 Write Data K+N−1
NOTE: Single Byte read is initiated by Master with P immediately following first data byte.
Figure 7. I
2
C Read Example
S WR A A S RD A A A NA P
Register address to Read specified
8bits
NOTE: If Register is not specified Master will begin read from current register. In this case only sequence showing
in Red bracket is needed
Single or multi byte read executed from current register location
(Single Byte read is initiated by Master with NA immediately following first data byte)
Read Data K+1 Read Data K+N−1
8bits 8bits 8bits
Slave Address Register Address K Read Data KSlave Address
From Master to Slave S Start Condition NA NOT Acknowledge (SDA High) RD Read =1
From Slave to Master A Acknowledge (SDA Low) WR Write = 0 P Stop Condition
