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SIC620ARCD-T1-GE3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
S14-2189, Rev. A 03-Nov-14
13
Document Number: 63589
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Step 5: Signal Routing
1. Route the PWM / ZCD_EN# / DSBL# / THWn signal
traces out of the top left corner next DrMOS pin 1.
2. PWM signal is very important signal, both signal and
return traces need to pay special attention of not letting
this trace cross any power nodes on any layer.
3. It is best to “shield” traces form power switching nodes,
e.g. V
SWH
, to improve signal integrity.
4. GL (pin 27) has been connected with GL pad internally
and does not need to connect externally.
Step 6: Adding Thermal Relief Vias
1. Thermal relief vias can be added on the V
IN
and P
GND
pads to utilize inner layers for high-current and thermal
dissipation.
2. To achieve better thermal performance, additional vias
can be put on V
IN
plane and P
GND
plane.
3. V
SWH
pad is a noise source and not recommended to put
vias on this plane.
4. 8 mil drill for pads and 10 mils drill for plane can be the
optional via size. Vias on pad may drain solder during
assembly and cause assembly issue. Please consult
with the assembly house for guideline.
Step 7: Ground Connection
1. It is recommended to make single connection between
C
GND
and P
GND
and this connection can be done on top
layer.
2. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane and separate them into C
GND
and P
GND
plane.
3. These ground planes provide shielding between noise
source on top layer and signal trace on bottom layer.
P
GND
C
GND
C
GND
V
IN
plane
P
GND
plane
V
SWH
P
GND
V
IN
C
GND
V
SWH
P
GND
C
GND
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
S14-2189, Rev. A 03-Nov-14
14
Document Number: 63589
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Multi-Phases VRPower PCB Layout
Following is an example for 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with
decoupling caps next to them. The inductors are placed as close as possible to the SiC620R and SiC620AR to minimize the
PCB copper loss. Vias are applied on all PADs (V
IN
, P
GND
, C
GND
) of the SiC620R and SiC620AR to ensure that both electrical
and thermal performance are excellent. Large copper planes are used for all the high current loops, such as V
IN
, V
SWH
, V
OUT
and P
GND
. These copper planes are duplicated in other layers to minimize the inductance and resistance. All the control signals
are routed from the SiC620R and SiC620AR to a controller placed to the north of the power stage through inner layers to avoid
the overlap of high current loops. This achieves a compact design with the output from the inductors feeding a load located to
the south of the design as shown in the figure.
Fig. 29 - Multi - Phase VRPower Layout Top View
Fig. 30 - Multi - Phase VRPower Layout Bottom View
V
OUT
P
GND
V
IN
V
IN
P
GND
V
OUT
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
S14-2189, Rev. A 03-Nov-14
15
Document Number: 63589
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
RECOMMENDED LAND PATTERN PowerPAK MLP55-31L
PACKAGE OUTLINE DRAWING MLP55-31L
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63589
.
Land pattern for MLP55-31LPackage outline top view, transparent
All dimensions in millimeters
1.75
0.1
0.4
0.75
24
1
0.3
0.3
0.5
1.15
1.13
31
1.35
5
0.57
2.02
23
16
0.75
15
0.5
0.18
0.35
0.35
0.65
0.5
9
0.35
0.3
1
5
0.35
0.15
1.42
0.33
0.07
0.42.08
0.55
1.2
2.15
3.05
0.3
0.33
0.75
1.6
3.5
0.3
0.65
0.58 0.5
8
(D2-4)
3.4
(D2-1)
1.03
(D2-5)
1.05
24
31
(K2) 0.22
(K1) 0.67
(D3) 0.3
(D2-2)
1.03
(D2-3)
1.92
9
15
16
23
8
1
24
31
9
15
16
23
8
1
(L)
0.4
(L)
0.4
(E2-2)
1.32
0.5 (e)
(E2-3)
1.98
(E3)
0.45
(E2-1)
4.2
(b)
0.25
33
33
32
35
0.40
0.40 0.40
0.40
0.45
15
16
0.40
0.40
0.40
0.40
0.30
1.030.57
1.92
1.03
23
24
31
1
8
9
3.80
0.50
1.98
0.25
1.10
0.6096
5.00
23
2431
9
15
16
1
8
0.6096
0.20
0.127
0.127
0.22
2.88
5.00
0.704.10
0.20
0.60
2.66
1.08
0.56
0.10
0.10
1.10 1.08 2.34
0.48
0.09
1.32
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

SIC620ARCD-T1-GE3

Mfr. #:
Buy SIC620ARCD-T1-GE3
Manufacturer:
Vishay / Siliconix
Description:
Gate Drivers 60A VRPwr PowerPak DRMos MLP55-31L
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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