DS1558W-TRL Datasheet DS1558W+, DS1558W+TRL, DS1558Y+TRL | P4-P6

DS1558

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D CR ON

S1 s n, year 2000-compliant (Y2KC), real-time clock/calendar with an RTC

alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all

registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC

registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD

fo at. Corrections for day of month and leap year are made automatically.

The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0–A18.

W n any the

ES IPTI

The D 558 i a full-functio

he of upper 16 address locations are accessed, the DS1558 inhibits CER and OER to the

S M, an dir DS1558 can be used

w SRA up addresses. Smaller SRAMs can be used, provided that the unused upper

address lines on the DS1558 are connected to V

The RTC registers are double-buffered into an internal and external set. The user has direct access to the

external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow

th ser to ess static data. Assuming the internal oscillator is turned on, the internal set of registers is

continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC

in ation is always maintained.

The DS1558 has interrupt (

RA d re ects reads and writes to the RTC registers within the DS1558. The

to 524,272 ith Ms

e u acc

form

IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity.

The IRQ / ter terrupt when the RTC register values

m h use grammed alarm values. The interrupt is always available while the device is powered from

th ystem ply, and it can be programmed to occur when in the battery-backed state to serve as a

wake-up. The

FT in rupt output can be used to generate an external in

atc r-pro

e s sup

system IRQ /FT output can also be used as a CPU watchdog timer. CPU activity is

monitored and an interrupt or reset output are activated if the correct activity is not detected within

programm i ower-down or failure

and hold the CPU ; the

ed lim ts. The DS1558 power-on reset can be used to detect a system p

in a safe reset state until normal power returns and stabilizes RST output is used

for this function.

T DS155 also tects the data in the clock

and SRAM against out-of-tolerance V conditions by inhibiting the

he 8 contains its own power-fail circuitry, which automatically pro

CCI

CE input when the V

supply

enters an out-of-tolerance condition. W

, the external battery is

s hed u ovides a high degree of

data security during unpredictable

levels.

hen V

CCI

goes below the level of V

pply energy to the clock and the external SRAM. This feature prwitc on to s

system operation brought on by low V

DS1558

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Figure 1. BLOCK DIAGRAM

Table 1. OPERATING MOD

CE OE WE

DQ0–DQ7 MODE POWER

X X High-Z Deselect Standby

X V

Write Active

OUT

Read Active

> V

High-Z Read Active

< V

X X X High-Z Deselect CMOS Standby

< V

X X X High-Z Data Retention Battery Current

DATA READ MODE

The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows

gh access to any valid address location. Valid data is available at the DQ pins within t

after

the last address input is stable, provided that

ripple-th

rou

and

access times are satisfied. If

access

et, valid data is available at the latter of chip-enable access (t

CEA

) or at output-enable

OEA

). The state of the data input/output pins (DQ) is controlled by

tim

es are not m

access time

CE and OE . If the

ated before t

, the data lines are driven to an intermediate state until t

. If the address

inputs are changed while

outputs are activ

CE and OE remain valid, output data remains valid for output-data hold time

), but then goes indeterminate until the next address acces

s. (tOH

NOTE: ANY U S THE RTC.NUSED UPPER ADDRESS PINS MUST BE CONNECTED TO V

TO PROPERLY ADDRES

DS1558

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DATA WRITE MODE

The DS1558 is in the write mode whenever

and

are in their active state. The

referenced to the latter occurring transition of

start of a write is

WE or CE . The addresses must be hel

the cycle.

d valid throughout

CE and WE must return inactive for a minimum of t prior to the initiation of a subsequent

read or write cycle. Data in must be valid t prior to the

end of the write and remain valid for t

afterward. In a typical application, the

signal is high during a write cycle. However,

can be active

ten If provided that care is taken with the data bus to avoid bus con tion. OE is low prior to WE

ress inputs. A low transitioning low, the data bus can become active with read data defined by the add

transition on WE then disables the outputs t

WEZ

after WE goes active.

DATA RETENTION MODE

The 5V device is fully accessible and data can be written and read only when V

However, when V

is below the power-fail point V

(point at which write prot

internal clock registers and SRAM are blocked from any access. When V falls below the batter

s greater than V

ection occurs), the

y switch

point V

(battery supply level), device power is switched from the V

pin to the backup battery. RTC

inal levels.

s greater than V

he device power is

t . If V

is greater

drops

is returned to

All control, data, and address signals must be powered down when V

is powered down.

558 internal clock

current is less than

g. No external protection components

are required, and none should be used. The DS1558 has two battery pins that operate independently; the

DS1558 selects the higher of the two inputs. If only one battery is used, the battery should be attached to

BAT1

, and V

BAT2

should be grounded.

INTERNAL BATTERY MONITOR

The DS1558 constantly monitors the battery voltage of the internal battery. The battery-low flag (BLF)

bit of the flags register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever

present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable.

POWER-ON RESET

A temperature-compensated comparator circuit monitors the level of V

. When V

falls to the power-

fail trip point, the

operation and SRAM data are m

aintained from the battery until V

is returned to nom

The 3.3V device is fully accessible and data can be written and read only when V

When V

falls below V

, access to the device is inhibited. If V

is less than V

, t

switched from V

o the internal backup lithium battery when V

drops below V

than V

, the device power is switched from V

to the internal backup lithium battery when V

below V

. RTC operation and SRAM data are maintained from the battery until

nominal levels.

BATTERY LONGIVITY

The battery lifetime is dependent on the RAM battery standby current and the DS1

oscillator current. The total battery current is I

OSC

+ I

CCO

. When V

is above V

, I

BAT

50nA. The DS1558 has an internal circuit to prevent battery chargin

RST signal (open drain) is pulled low. When V

returns to nominal levels, the RST

signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is

independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

DS1558W-TRL

Mfr. #:

Buy DS1558W-TRL

Manufacturer:

Maxim Integrated

Description:

Real Time Clock

Lifecycle:

New from this manufacturer.

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DS1558W-TRL

DS1558W-TRL

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