DS1558
8 of 18
of double-buffered
ad without register
tinue while in this
he control register
t halt is issued,
alt com
t ume within 1 second after the read bit is set to
s. The read bit m inimum of 500 s to ensure the extern
e the read bit, halts
updates to the 7FFF8h–7FFFFh registers. After setting the write bit to a 1, RTC registers can be loaded
rite bit to a 0 then
resume.
y of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
load for which the crystal was
by temperature shifts. External
o the oscillator circuit can result in the clock running fast. Refer to Application
n.
READING THE CLOCK
When reading the RTC data, it is recomme ed to halt updates to the external set
RTC registers. This puts the external registers into a static state, allowing data to be re
values changing during the read process. Normal updates to the internal registers con
state. External updates are halted when a 1 is written into the read bit, B6 of t
(7FFF8h). As long as a 1 remains in the control register read bit, updating is halted. Af
the registers reflect the RTC count (day, date, and time) that was current at the moment
is issued. Normal updates to the external se f registers
nd
o
u
er a
the h mand
al
re
st be a 0 for a m
s
a 0 for a minimum of 500
registers are updated.
SETTING THE CLOCK
The MSB bit, B7, of the control register is the write bit. Setting the write bit to a 1, lik
with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the w
transfers the values written to the internal RTC registers and allows normal operation to
CLOCK ACCURACY
The accurac
between the capacitive load of the oscillator circuit and the capacitive
trimmed. Additional error is added by the crystal-frequency drift caused
circuit noise coupled int
Note 58 “Crystal Considerations with Dallas Real-Time Clocks” for detailed informatio
FREQUENCY TEST MODE
The DS1558 frequency test mode uses the open-drain IRQ /FT output. With the oscillator running, the
IRQ /FT output toggles at 512Hz when the FT bit is a 1, the alarm-flag enable bit (AE) is a 0, and the
r the watchdog register is reset (register 7FFF7h = 00h). The watchdog-enable bit (WDS) is a 1, o
IRQ
/FT
of the 32.768kHz output and the frequency test mode can be used as a measure of the actual frequency
RTC oscillator. The
IRQ /FT pin is an open-drain output that requires a pullup resistor for proper
operation. The FT bit is cleared to a 0 on power-up.
. Register 7FFF6h
The AE and ABE
bits must be set as described below for the
USING THE CLOCK ALARM
The alarm settings and control for the DS1558 reside within registers 7FFF2h–7FFF5h
contains two alarm-enable bits: alarm enable (AE) and alarm in backup enable (ABE).
IRQ
/FT output to be activated for a matched alarm condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1558 is in the battery-backed state of
operation to serve as a system wake-up. Alarm mask bits AM1–AM4 control the alarm mode. Table 3
ions not listed in the table default to the once-per-second mode to
notify the user of an incorrect alarm setting.
shows the possible settings. Configurat
