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AR0231AT7C00XUEA0-DRBR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
© Semiconductor Components Industries, LLC, 2016
September, 2017 − Rev. P6
1 Publication Order Number:
AR0231/D
AR0231AT
Advance Information
AR0231AT 1/2.7-inch 2.3 Mp
Digital Image Sensor
Description
The AR0231AT from ON Semiconductor is a 1/2.7−inch CMOS
digital image sensor with a 1928(H) × 1208 (V) active−pixel array. It
captures images in either linear, high dynamic range, or LFM modes,
with a rolling−shutter readout. The LFM mode eliminates high
frequency LED flicker in the image allowing Traffic Sign Reading
(TSR) algorithms to operate in all lighting conditions. It includes
sophisticated camera functions such as in−pixel binning, windowing
and both video and single frame modes. It is designed for both low
light and high dynamic range scene performance, with sensor fault
detection features that can enable ASIL B compliance for the camera
system. It is programmable through a simple two−wire serial interface.
The AR0231AT produces extraordinarily clear, sharp digital pictures,
and its ability to capture both continuous video and single frames
makes it the perfect choice for a wide range of applications, including
automotive ADAS, automotive scene viewing, and 1080p HDR video.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Typical Value
Optical Format 1/2.7−inch (6.82 mm)
Maximum Resolution 1928 × 1208 (2.3 Mp)
Shutter Type Electronic Rolling Shutter (ERS)
Pixel Size
3 mm
Pixel Output Interfaces Up to 4−lane HiSPi with SLVS and HiVCM MIPI
CSI−2
14−bit parallel
Output Formats 12−bit Uncompressed Linear
20−bit Uncompressed HDR
10−bit Companded Linear
16−bit, 14−bit, or 12−bit Companded HDR
Control Interface 2−wire, Serial Control 100 kHz/1 MHz
Input Clock Range 6−50 MHz in PLL Mode
6−88 MHz Max in PLL−bypass Mode
Maximum Frame Rate Up to 40 fps at 1928 × 1208 / 3−exposure
Up to 60 fps at 1928 × 1208 / 2−exposures
and Linear
Output Pixel Clock
Maximum
88 MHz
Responsivity 34 ke−/lux−sec
SNR
MAX
42.8 dB
Max Dynamic Range > 120 dB
Operating Temp. Range
–40°C to 125°C Junction
Supply Voltage I/O 1.8 V or 2.8 V
Digital 1.2 V
Analog 2.8 V
HiSPi 0.4 V or 1.8 V
Power Consumption < 350 mW Typical (1928 × 1208, 30 fps)
Packaging Options 11 × 10 iBGA Bare Die
www.onsemi.com
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION
IBGA121 10x11
CASE 503BG
Features
• Key Technologies:
♦ Automotive Grade Backside
Illuminated Pixel
♦ LED Flicker Mitigation Mode
♦ Sensor Fault Detection for ASIL−B
Compliance
♦ Up to 4−exposure HDR at 1928 × 1208
and 30 fps or 3−exposure HDR at
1928 × 1208 and 40 fps
• Latest 3.0 mm Back Side Illuminated (BSI
)
Pixel with ON Semiconductor DR−Pixt
Technology
• Data Interfaces: up to 4−lane MIPI CSI−2,
Parallel, or up to 4−lane High Speed Pixel
Interface (HiSPi) Serial Interface (SLVS
and HiVCM)
• Advanced HDR with Flexible Exposure
Ratio Control
This document contains information on a new
product. Specifications and information herein
are subject to change without notice.
This document, and the information contained herein
,
is CONFIDENTIAL AND PROPRIETARY and the
property of Semiconductor Components Industries
,
LLC., dba ON Semiconductor. It shall not be used
,
published, disclosed or disseminated outside of the
Company, in whole or in part, without the written
permission of ON Semiconductor. Reverse
engineering of any or all of the information contained
herein is strictly prohibited.
E 2017, SCILLC. All Rights Reserved.
AR0231AT
CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
www.onsemi.com
2
Features (Continued)
• LED Flicker Mitigation (LFM) Mode
• Selectable Automatic or User Controlled Black Level
Control
• Frame to Frame Switching among up to 4 Contexts to
Enable Multi−function Systems
• Spread−spectrum Input Clock Support
• Multi−Camera Synchronization Support
• Multiple CFA Options
Applications
• Automotive ADAS
• 1080p30 Video Applications
• High Dynamic Range Imaging
• Mirror Replacement
• ADAS + Viewing Fusion
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
Description
AR0231AT7C00XUEA0−DRBR−E RGB, iBGA, Dry Pack without protective film
AR0231AT7C00XUEA0−DPBR−E RGB, iBGA, Dry Pack
AR0231AT7R00XUEA0−DRBR−E RCCC, iBGA, Dry Pack without protective film
AR0231AT7R00XUEA0−DPBR−E RCCC, iBGA, Dry Pack
AR0231AT7B00XUEA0−DRBR−E RCCB, iBGA, Dry Pack without protective film
AR0231AT7B00XUEA0−DPBR−E RCCB, iBGA, Dry Pack
AR0231AT7C00XUD20−E RGB, Bare Die
AR0231AT7R00XUD20−E RCCC, Bare Die
AR0231AT7B00XUD20−E RCCB, Bare Die
AR0231AT7C00XUEAH3−GEVB RGB, Headboard
AR0231AT7R00XUEAH3−GEVB RCCC, Headboard
AR0231AT7B00XUEAH3−GEVB RCCB, Headboard
AR0231AT7C00XUEAD3−GEVK RGB, Demo Kit
AR0231AT7R00XUEAD3−GEVK RCCC, Demo Kit
AR0231AT7B00XUEAD3−GEVK RCCB, Demo Kit
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com
.
GENERAL DESCRIPTION
The AR0231AT from ON Semiconductor can be operated
in its default mode or programmed for frame size, exposure,
gain, and other parameters. The default mode output is
a 1208p−resolution image at 40 frames per second (fps) in
3−exposure HDR mode and 30 fps in 4−exposure HDR
mode through the serial output ports. In linear mode, it
outputs 12−bit or 14−bit uncompressed, or 10−bit
compressed raw data, using either the parallel or serial
output ports. In high dynamic range (HDR) mode, it outputs
12, 14−, or 16−bit compressed data using parallel output, or
12−, 14−, or 16−bit compressed or 20−bit linearized data
using the serial port (HiSPi or MIPI). The device may be
operated in video (master) mode or in single frame trigger
mode. The LFM mode is used to minimize the impact of
LED flicker for applications where there is dynamic LED
lighting, such as TSR, and is output in linear mode.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
The AR0231AT has additional ASIL features, including
but not limited to: two on−board independent temperature
sensor, startup tests, memory BIST, analog and digital CRC,
and test patterns. Optional register information and
histogram statistic information can be embedded in the first
and last 2 lines of the image frame.
The sensor is designed to operate in a wide temperature
range (−40
°C to + 125°C).
AR0231AT
CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
www.onsemi.com
3
FUNCTIONAL OVERVIEW
The AR0231AT is a 1/2.7 inch progressive−scan sensor
that generates a stream of pixel data at a constant frame rate.
It uses an on−chip, phase−locked loop (PLL) that can be
optionally enabled to generate all internal clocks from
a single master input clock running between 6 and 50 MHz.
The PLL can also be bypassed in parallel mode, which
allows for the input clock to run between 6 and 88 MHz. The
maximum output pixel rate is 750 Mb/s in serial modes, and
88 Mp/s in parallel modes, corresponding to a clock rate of
88 MHz. Figure 1 shows a block diagram of the sensor.
Figure 1. Block Diagram
Control Registers
Analog Processing and
A/D Conversion
Active Pixel Sensor
(APS)
Array
Pixel Data Path
(Signal Processing)
Timing and Control
(Sequencer)
Stats Engine
OTPM Memory PLL
External
Clock
Serial
Output
Trigger
Two-wire
Serial
Interface
Power
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 2.3 Mp BSI Active−Pixel Sensor array. The
timing and control circuitry sequences through the rows of
the array, resetting and then reading each row in turn. In the
time interval between resetting a row and reading that row,
the pixels in the row integrate incident light. The exposure
is controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog−to−digital converter (ADC). The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The sensor also offers a high dynamic range
mode of operation where multiple images are combined
on−chip to produce a single image at 20−bit per pixel value.
A compressing mode is further offered to allow this 20−bit
pixel value to be transmitted to the host system as a 12− or
14− or 16−bit value with close to zero loss in image quality.
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AR0231AT7C00XUEA0-DRBR

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Description:
2MP 1/3 CIS SO
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