AR0231AT
CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
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13
Table 7. TWO-WIRE SERIAL BUS CHARACTERISTICS
(f
EXTCLK
= 27 MHz; V
DD
= 1.8 V; V
DD
_IO = 2.8 V; V
AA
= 2.8 V; V
AA
_PIX = 2.8 V; V
DD
_PLL = 2.8 V; T
A
= 25°C)
Symbol
Parameter
Standard Mode Fast Mode
Unit
Min Max Min Max
f
SCL
S
CLK
Clock Frequency 0 100 0 1000 kHz
t
HD;STA
Hold Time (Repeated) START Condition.
After this period, the first clock pulse is generated
4.0 − 0.6 −
ms
t
LOW
LOW Period of the S
CLK
Clock 4.7 − 1.3 −
ms
t
HIGH
HIGH Period of the S
CLK
Clock 4.0 − 0.6 −
ms
t
SU;STA
Set−up Time for a Repeated START Condition 4.7 − 0.6 −
ms
t
HD;DAT
Data Hold Time 0
(Note 12)
3.45
(Note 13)
0
(Note 14)
0.9
(Note 13)
ms
t
SU;DAT
Data Set−up Time 250 − 100 (Note 14) − ns
t
r
Rise Time of both S
DATA
and S
CLK
Signals − 1000 20 + 0.1 Cb
(Note 15)
300 ns
t
f
Fall Time of both S
DATA
and S
CLK
Signals − 300 20 + 0.1 Cb
(Note 15)
300 ns
t
SU;STO
Set−up Time for STOP Condition 4.0 − 0.6 −
ms
t
BUF
Bus Free Time between a STOP and START Condition 4.7 − 1.3 −
ms
Cb Capacitive Load for each Bus Line − 400 − 400 pF
C
IN_SI
Serial Interface Input Pin Capacitance − 3.3 − 3.3 pF
C
LOAD_SD
S
DATA
Max Load Capacitance − 30 − 30 pF
R
SD
S
DATA
Pull−up Resistor 1.5 4.7 1.5 4.7
kW
9. This table is based on I
2
C standard (v2.1 January 2000). Philips Semiconductor.
10.Two−wire control is I
2
C−compatible.
11. All values referred to V
IHmin
= 0.9 V
DD
and V
ILmax
= 0.1 VDD levels. Sensor EXCLK = 27 MHz.
12.A device must internally provide a hold time of at least 300 ns for the S
DATA
signal to bridge the undefined region of the falling edge of S
CLK
.
13.The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the S
CLK
signal.
14.A Fast−mode I
2
C−bus device can be used in a Standard−mode I
2
C−bus system, but the requirement t
SU;DAT
250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the S
CLK
signal. If such a device does stretch the LOW period
of the S
CLK
signal, it must output the next data bit to the S
DATA
line t
r
max + t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard−mode
I
2
C−bus specification) before the S
CLK
line is released.
15.Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the AR0231AT launches pixel data, FV, and
LV with the falling edge of PIXCLK. The expectation is that
the user captures D
OUT
[13:0], FV, and LV using the rising
edge of PIXCLK.
See Figure 9 below and Table 8 for I/O timing (AC)
characteristics.
Figure 9. I/O Timing Diagram
EXTCLK
PIXCLK
Data[13:0]
LINE_VALID/
FRAME_VALID
Pxl_0 Pxl_1 Pxl_2 Pxl_n
t
PF
t
PL
t
FP
t
RP
t
F
t
R
90% 90% 90% 90%
10% 10% 10% 10%
t
EXTCLK
t
PD
t
PLH
t
PFH
FRAME_VALID Leads LINE_VALID
by 6 PIXCLKs
FRAME_VALID Trails LINE_VALID
by 6 PIXCLKs
