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Figure 7. Grid−ROI, Configuration 1; x_grid_status=0x3; y_grid_status=0x3
X Output Size
Y Output Size
X = 0, Y = 0 Y = Y
offset1
Y = Y
offset2
Y = Y
offset3
X = X
offset
1
X = X
offset
2
X = X
offset
3
(0, 0) (0, 1) (0, 2) (0, 3)
(1, 0) (1, 1) (1, 2) (1, 3)
(2, 0) (2, 1) (2, 2) (2, 3)
(3, 0) (3, 1) (3, 2) (3, 3)
Black Level Control/Correction
Black level correction can optionally be automatically
controlled by the AR0231AT; the default setting is for
automatic black level calibration to be enabled. The
automatic black level correction measures the average value
of pixels from a set of optically black pixel rows in the image
sensor. The pixels are averaged as if they were light sensitive
and passed through the appropriate gain. This line average
is then digitally low−pass filtered over many frames to
remove temporal noise and random instabilities associated
with this measurement. The optically black lines may be
read out, bypassing the datapath, for off−chip analysis. The
automatic black level correction can be disabled and the
black level set manually via register settings. Manual black
level settings are frame synchronized to the next start of
frame.
Row and Column Correction
Row and column noise correction is applied automatically
by the image sensor on a frame by frame basis.
Re−triggering of correction circuits due to settings or
temperature changes are not necessary. The digital gain can
be applied before HDR linearization for white balancing,
and after HDR linearization for increasing scene brightness.
Defective Pixel Tracking/Correction
Defective Pixel Correction (DPC) is intended to
compensate or tag defective pixels by replacing their value
with a value based on the surrounding pixels, or tagging
them by assigning them a ‘0’ value. The defect pixel
correction feature supports up to 200 defects. The locations
of defective pixels are stored in a table on chip during the
manufacturing process; this table is accessible through the
two−wire serial interface. There is no provision for later
augmenting the defect table entries. The DPC algorithm is
one−dimensional, calculating the resulting averaged pixel
value based on nearby pixels within a row. The algorithm
distinguishes between color and monochrome parts; for
color parts, the algorithm uses nearest neighbor in the same
color plane. The defect pixel correction algorithm may be
disabled. (Note that the outgoing defect specification for the
AR0231AT assumes the defect correction is disabled). The
defect pixels identified during manufacture can be read from
on−chip ROM via the 2−wire control interface.
Analog/Digital Gains
A programmable analog gain of 0.125x to 8x applied
simultaneously to all color channels will be featured along
with a digital gain of 1x to 16x that may be configured on a
per color channel basis. Future releases will have an option
to separate the digital gain for use as an AWB function and
as a global gain.
Skipping/Binning Modes
The AR0231AT supports subsampling. Subsampling
allows the sensor to read out a smaller set of active pixels by
either skipping, binning, or summing pixels within the
readout window. Horizontal binning is achieved in the
digital readout. The sensor will sample the combined two
adjacent pixels within the same color plane. Vertical row
binning is applied in the pixel readout. Row binning can be
configured as two rows within the same color plane. Pixel
skipping can be configured up to two in both the x−direction
and y−direction. Skipping pixels in the x−direction will not
reduce the row time. Skipping pixels in the y direction will
reduce the number of rows from the sensor effectively
reducing the frame time. Skipping will introduce image
artifacts from aliasing. The AR0231AT supports row wise
vertical binning. Row wise vertical summing is not
supported.
CFA Type Identification
CFA type (e.g. RGB, mono, etc.) may be determined by
reading an identification register via the 2−wire control
interface.
ASIL/ISO26262 Support Features
The AR0231AT incorporates many features to assist
ASIL−B system compliance to be achieved by a system that
integrates it. Please refer to the AR0231AT Safety Manual
for more information.
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SYSTEM INTERFACES
This section describes the AR0231AT interfaces. Note
that all output port options may not be available on all
packaging options.
HiSPi Pixel Output Port
The AR0231AT provides a 4−lane HiSPi pixel output port
with support for SLVS and HiVCM modes. Supported
configurations are described in Table 4. Additional
information is provided in the ON Semiconductor HiSPi
Protocol and Physical Layer documents.
Table 4. HISPI PROTOCOL SUPPORT
Lanes
Width Data Type Protocols Max. Mbps/Lane Notes
1, 2, or 4 20−bit Bayer/RAW SP−packetized
SP−streaming
Streaming−S
750 Mbps HDR Output Mode
(Uncompressed)
1, 2, or 4 16−bit Bayer/RAW SP−packetized
SP−streaming
Streaming−S
750 Mbps HDR Output Mode
(Compressed)
1, 2, or 4 14−bit Bayer/RAW SP−packetized
SP−streaming
Streaming−S
750 Mbps HDR Output Mode
(Compressed)
1, 2, or 4 12−bit Bayer/RAW SP−packetized
SP−streaming
Streaming−S
750 Mbps SDR (Linear) Mode
MIPI CSI−2 Pixel Output Port
The AR0231AT provides a 4−lane MIPI CSI−2 pixel
output port. The data protocol support is per Table 5. Please
contact ON Semiconductor for additional information.
Table 5. MIPI PROTOCOL SUPPORT
Lanes
Width Data Type Protocols Max. Mbps/Lane Notes
1, 2, or 4 20−bit Bayer/RAW SP−packetized
SP−streaming
520 Mbps HDR Output Mode
(Uncompressed)
1, 2, or 4 16−bit Bayer/RAW SP−packetized
SP−streaming
520 Mbps HDR Output Mode
(Compressed)
1, 2, or 4 14−bit Bayer/RAW SP−packetized
SP−streaming
520 Mbps HDR Output Mode
(Compressed)
1, 2, or 4 12−bit Bayer/RAW SP−packetized
SP−streaming
520 Mbps SDR (Linear) Mode
Parallel Pixel Output Port
The AR0231AT provides a 14−bit data pixel output port
with frame and line valid signals. HDR data is companded
to 14−bit or 12−bit, and 12−bit SDR (non−HDR) data may
be output via this port.
Note that the parallel port cannot be used to output
combinations of individual T1/T2/T3/T4 exposures on a per
frame basis.
Line Interleaved Output
The AR0231AT will have the capability to output the T1,
T2, T3, and T4 exposures separately, in a line interleaved
format. The purpose of this is to enable off chip HDR linear
combination and processing.
Embedded data and statistics are also supported in line
interleaved mode. See the AR0231AT Developer Guide for
more information.
Two−Wire Sensor Control Interface
The two−wire serial interface bus enables read/write
access to control and status registers within the AR0231AT.
The interface protocol uses a master/slave model in which
a master controls one or more slave devices. The sensor acts
as a slave device. The master generates a clock (S
CLK
) that
is an input to the sensor and is used to synchronize transfers.
Data is transferred between the master and the slave on
a bidirectional signal (S
DATA
). S
DATA
is pulled up to
V
DD
_IO off−chip by a 1.5 kW resistor. Either the slave or
master device can drive S
DATA
LOW−the interface protocol
determines which device is allowed to drive S
DATA
at any
given time. The protocols described in the two−wire serial
interface specification allow the slave device to drive S
CLK
LOW; the AR0231AT uses S
CLK
as an input only and
therefore never drives it LOW.
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ELECTRICAL SPECIFICATIONS
Table 6. ELECTRICAL SPECIFICATIONS
Symbol Definition Min Nom Max Unit
V
DD
Core Digital Voltage 1.14 1.2 1.26 V
V
DD
_IO I/O Digital Voltage 1.7/2.52 1.8/2.8 1.9/3.0 V
V
AA
Analog Voltage 2.6 2.8 3.0 V
V
AA
_PIX Pixel Supply Voltage 2.6 2.8 3.0 V
V
DD
_PHY PHY Supply Voltage 1.14 1.2 2.16 V
V
DD
_IO_PHY Serial PHY Supply Voltage 1.7 /2.52 1.8/2.8 1.9/3.0 V
V
DD
_SLVS HiSPi Supply Voltage (SLVS) 0.3 0.4 0.6 V
V
DD
_SLVS HiSPi Supply Voltage (HiVCM) 1.14 1.2 2.16 V
8. V
AA
_PIX must always be equal to V
AA
.
Power Up
For controlled power up, RESET_BAR pin must be
asserted (low) before supplies can be sequenced up in any
order (V
DD
_IO must be brought up before V
AA
unless all
supplies are brought up at the same time). Once all supplies
are valid, RESET_BAR is deasserted (high), the part will
begin boot−up on EXTCLK.
Power Down
For controlled power down, streaming must be first
disabled. The RESET_BAR pin must be asserted (low)
before any external supplies are removed. The V
AA
supply
must be sequenced off before the V
DD
_IO supply, unless all
supplies are powered down at the same time.
Typical Power Down Sequence:
1. De−assert Streaming: Set software standby mode
(mode_select = 0) register.
2. Wait till the end of the current frame (or
end−of−line if so configured).
3. Configure I/O for “hold” if desired. “Hold” state
requires maintaining V
DD
_IO; however.
4. Set RESET_BAR = 0 (Hard Standby, low−leakage
state).
5. Wait t
0
power−down delay.
6. Power off supplies in prescribed order. For “hold”
I/O state, do not power off V
DD
_IO supply.
Two−Wire Serial Register Interface
The electrical characteristics of the two−wire serial
register interface (S
CLK
, S
DATA
) are shown in Figure 8 and
Table 7.
Figure 8. Two−wire Serial Bus Timing Parameters
S
DATA
S
CLK
S Sr P S
t
f
t
r
t
f
t
r
t
SU;DAT
t
HD;STA
t
SU;STO
t
SU;STA
t
BUF
t
HD;DAT
t
HIGH
t
LOW
t
HD;STA
NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.

AR0231AT7C00XUEA0-DRBR

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