OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7862ARZ-3REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD7862
–9–
REV. 0
and fourth read pulses, after the second conversion and A0 high,
access the result from Channel B (V
B1
and V
B2
respectively). A0’s
state can be changed any time after the
CONVST goes high,
i.e., track/holds into hold, and 400 ns prior to the next falling
edge of
CONVST. Data is read from the part via a 12-bit
parallel data bus with standard
CS and RD signal, i.e., the read
operation consists of a negative going pulse on the
CS pin
combined with two negative going pulses on the
RD pin (while
the
CS is low), accessing the two 12-bit results. Once the read
operation has taken place, a further 300 ns should be allowed
before the next falling edge of
CONVST to optimize the settling
of the track/hold amplifier before the next conversion is initiated.
With the internal clock frequency at its maximum (3.7 MHz—not
accessible externally), the achievable throughput rate for the
part is 3.6 µs (conversion time) plus 100 ns (read time) plus
0.3 µs (acquisition time). This results in a minimum throughput
time of 4 µs (equivalent to a throughput rate of 250 kHz).
Read Options
Apart from the read operation described above and displayed in
Figure 5a, other
CS and RD combinations can result in
different channels/inputs being read in different combinations.
Suitable combinations are shown in Figures 5b through 5d.
V
A1
V
A2
CS
RD
DATA
Figure 5b. Read Option A
Figure 5c. Read Option B
V
A1
V
B1
A0
CS
RD
DATA
Figure 5d. Read Option C
OPERATING MODES
Mode 1 Operation (High Sampling Performance)
The timing diagram in Figure 5a is for optimum performance in
operating mode 1 where the falling edge of
CONVST starts
conversion and puts the track/hold amplifiers into their hold
mode. This falling edge of
CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 3.6 µs max after the falling edge of
CONVST, and new
data from this conversion is available in the output latch of the
AD7862. A read operation accesses this data. If the multiplexer
select A0 is low, the first and second read pulses after the first
conversion access the result from Channel A (V
A1
and V
A2
V
A1
V
A2
V
B1
V
B2
t
3
t
1
t
2
t
4
t
5
t
6
t
CONV
= 3.6µs
t
7
CONVST
BUSY
A0
CS
RD
DATA
300ns
400ns
Figure 5a. Mode 1 Timing Operation Diagram for High Sampling Performance
AD7862
–10–
REV. 0
respectively). The third and fourth read pulses, after the second
conversion and A0 high, access the result from Channel B (V
B1
and V
B2
respectively). Data is read from the part via a 12-bit
parallel data bus with standard
CS and RD signals. This data
read operation consists of negative going pulse on the
CS pin
combined with a negative going pulse on the
RD pin; this repeated
twice will access the two 12-bit results. For the fastest throughput
rate (with an internal clock of 3.7 MHz), the read operation will
take 100 ns. The read operation must be complete at least 300 ns
before the falling edge of the next
CONVST, and this gives a total
time of 4 µs for the full throughput time (equivalent to 250 kHz).
This mode of operation should be used for high sampling
applications.
Mode 2 Operation (Auto Sleep After Conversion)
The timing diagram in Figure 6 is for optimum performance in
Operating Mode 2 where the part automatically goes into sleep
mode once BUSY goes low after conversion and “wakes-up”
before the next conversion takes place. This is achieved by keeping
CONVST low at the end of the second conversion, whereas it
was high at the end of the second conversion for Mode 1 opera-
tion. The operation shown in Figure 6 shows how to access data
from both Channels A and B followed by the Auto Sleep mode.
One can also setup the timing to access data from Channel A
only or Channel B only (see Read Options section on previous
page) and then go into Auto-Sleep mode. The rising edge of
CONVST “wakes-up” the part. This wake-up time is 2.5 µs
when using an external reference and 5 ms when using the
internal reference at which point the Track/Hold amplifier’s go
into their hold mode, provided the
CONVST has gone low. The
conversion takes 3.6 µs after this, giving a total of 6 µs (external
reference, 5.0035 ms for internal reference) from the rising edge
of
CONVST to the conversion being complete, which is
indicated by the BUSY going low. Note that since the wake-up
time from the rising edge of
CONVST is 2.5 µs, if the CONVST
pulse width is greater than 2.5 µs, the conversion will take more
than the 6 µs (2.5 µs wake-up time + 3.6 µs conversion time)
shown in the diagram from the rising edge of
CONVST. This is
because the track/hold amplifiers go into their hold mode on
the falling edge of
CONVST, and the conversion will not be
complete for a further 3.6 µs. In this case the BUSY will be the
best indicator for when the conversion is complete. Even though
the part is in sleep mode, data can still be read from the part.
The read operation is identical to Mode 1 operation and must
also be complete at least 300 ns before the falling edge of the
next
CONVST to allow the track/hold amplifiers to have enough
time to settle. This mode is very useful when the part is convert-
ing at a slow rate, as the power consumption will be significantly
reduced from that of Mode 1 operation.
DYNAMIC SPECIFICATIONS
The AD7862 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as Integral and Differential Nonlinearity. These ac specifications
are required for the signal processing applications such as phased
array sonar, adaptive filters and spectrum analysis. These applica-
tions require information on the ADC’s effect on the spectral
content of the input signal. Hence, the parameters for which the
AD7862 is specified include SNR, harmonic distortion, inter-
modulation distortion and peak harmonics. These terms are
discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (f
S
/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to noise ratio for a sine wave
input is given by
SNR = (6.02N + 1.76) dB (1)
where N is the number of bits.
Thus for an ideal 12-bit converter, SNR = 74 dB.
V
A1
V
A2
V
B1
V
B2
t
3
t
CONV
= 3.6µs
CONVST
BUSY
A0
CS
RD
DATA
300ns
400ns
t
3
2.5µs*/5ms**
WAKE-UP
TIME
t
CONV
= 3.5µs
**WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 2.5µs
**WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms
Figure 6. Mode 2 Timing Where Automatic Sleep Function Is Initiated
AD7862
–11–
REV. 0
Figure 7 shows a histogram plot for 8192 conversions of a dc
input using the AD7862 with 5 V supply. The analog input was
set at the center of a code transition. It can be seen that all the
codes appear in the one output bin indicating very good noise
performance from the ADC.
746 756747 748 749 750 751 752 753 754 755
9000
8000
0
4000
3000
2000
1000
6000
5000
7000
Figure 7. Histogram of 8192 Conversions of a DC Input
The same data is presented in Figure 8 as in Figure 7 except
that in this case the output data read for the device occurs
during conversion. This has the effect of injecting noise onto the
die while bit decisions are being made and this increases the
noise generated by the AD7862. The histogram plot for 8192
conversions of the same dc input now shows a larger spread of
codes. This effect will vary depending on where the serial clock
edges appear with respect to the bit trials of the conversion
process. It is possible to achieve the same level of performance
when reading during conversion as when reading after conver-
sion depending on the relationship of the serial clock edges to
the bit trial points.
The output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the V
AX/BX
input that is
sampled at a 245.76 kHz sampling rate. A Fast Fourier Trans-
form (FFT) plot is generated from which the SNR data can be
obtained. Figure 9 shows a typical 2048 point FFT plot of the
AD7862 with an input signal of 10 kHz and a sampling fre-
quency of 245.76 kHz. The SNR obtained from this graph is
72.95 dB. It should be noted that the harmonics are taken into
account when calculating the SNR.
745 755746 747 748 749 750 751 752 753 754
0
4000
3000
2000
1000
6000
5000
7000
Figure 8. Histogram of the 8192 Conversions with Read
During Conversion
–0
–120
0 12.2k10k 30k 50k 70k 90k
–20
–40
–60
–80
–100
–10
–30
–50
–70
–90
–110
100k
F
SAMPLE
= 245760
F
IN
= 10kHz
SNR = –72.95dB
THD = –89.99dB
Figure 9. AD7862 FFT Plot
Effective Number of Bits
The formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N).
N =
SNR −1. 76
6.02
(2)
The effective number of bits for a device can be calculated
directly from its measured SNR.
Figure 10 shows a typical plot of effective number of bits versus
frequency for an AD7862BN with a sampling frequency of
245.76 kHz. The effective number of bits typically falls between
11.6 and 10.6 corresponding to SNR figures of 71.59 dB and
65.57 dB.
0 1000200 400 600 800
10.2
11.4
11.2
11.0
10.8
11.8
11.6
12.0
10.6
10.4
FREQUENCY – kHz
ENOB
Figure 10. Effective Numbers of Bits vs. Frequency
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD7862, THD is defined as
THD dB
()
=20 log
V
2
2
+V
3
2
+V
4
2
+V
5
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
and V
5
are the rms amplitudes of the second through the
sixth harmonic. The THD is also derived from the FFT plot of
the ADC output spectrum.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7862ARZ-3REEL

Mfr. #:
Buy AD7862ARZ-3REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Simult Sampling Dual 250kSPS 12-Bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet