AD7862ARZ-3REEL Datasheet AD7862ARSZ-2, AD7862ARZ-10, AD7862ARSZ-3 | P13-P15

AD7862

–12–

REV. 0

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for

which neither m or n are equal to zero. For example, the second

order terms include (fa + fb) and (fa – fb) while the third order

terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).

Using the CCIF standard where two input frequencies near the

top end of the input bandwidth are used, the second and third

order terms are of different significance. The second order terms

are usually distanced in frequency from the original sine waves

while the third order terms are usually at a frequency close to

the input frequencies. As a result, the second and third order

terms are specified separately. The calculation of the inter-

modulation distortion is as per the THD specification where it is

the ratio of the rms sum of the individual distortion products to

the rms amplitude of the fundamental expressed in dBs. In this

case the input consists of two, equal amplitude, low distortion

sine waves. Figure 11 shows a typical IMD plot for the AD7862.

–0

–120

0 12.3k10k 30k 50k 70k 90k

–20

–40

–60

–80

–100

–10

–30

–50

–70

–90

–110

100k

INPUT FREQUENCIES

F1 = 50010 Hz

F2 = 49110 Hz

SAMPLE

= 245760 Hz

SNR = –60.62dB

THD = –89.22dB

IMD:

2ND ORDER TERM –88.44 dB

3RD ORDER TERM –66.20 dB

Figure 11. AD7862 IMD Plot

Peak Harmonic or Spurious Noise

Harmonic or spurious noise is defined as the ratio of the rms

value of the next largest component in the ADC output spec-

trum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification will be

determined by the largest harmonic in the spectrum, but for

parts where the harmonics are buried in the noise floor, the peak

will be a noise peak.

AC Linearity Plot

When a sine wave of specified frequency is applied to the V

input of the AD7862, and several million samples are taken, a

histogram showing the frequency of occurrence of each of the

4096 ADC codes can be generated. From this histogram data, it

is possible to generate an ac integral linearity plot as shown in

Figure 12. This shows very good integral linearity performance

from the AD7862 at an input frequency of 10 kHz. The absence

of large spikes in the plot shows good differential linearity. Sim-

plified versions of the formulas used are outlined below.

INL(i) =

()

−Vo

()

×4096

()

−Vo

()













−i

where INL(i) is the integral linearity at code i. V(f

) and V(o)

are the estimated full-scale and offset transitions, and V(i) is the

estimated transition for the i

code.

V(i), the estimated code transition point is derived as follows:

V(i) =−A×Cos

π×cum i

()













where A is the peak signal amplitude, N is the number of

histogram samples

and cum i

()

= Vn

()

n=0

∑

occurrences

–0.1

–0.2

–0.3

–0.4

–0.5

0.5

0.4

0.3

0.2

0.1

LSB

= 10 kHz

= 245.760 kHz

= 25°C

Figure 12. AD7862 AC INL Plot

Power Considerations

In the automatic power-down mode the part may be operated at

a sample rate that is considerably less than 200 kHz. In this

case, the power consumption will be reduced and will depend

on the sample rate. Figure 13 shows a graph of the power

consumption versus sampling rates from 100 Hz to 90 kHz in

the automatic power-down mode. The conditions are 5 V

supply 25°C, and the data was read after conversion.

0.1 9010 20 30 40

FREQUENCY – kHz

POWER – mW

50 60 70 80

Figure 13. Power vs. Sample Rate in Auto Power-Down

Mode

AD7862

–13–

REV. 0

MICROPROCESSOR INTERFACING

The AD7862 high speed bus timing allows direct interfacing to

DSP processors as well as modern 16-bit microprocessors.

Suitable microprocessor interfaces are shown in Figures 14

through 18.

AD7862–ADSP-2100 Interface

Figure 14 shows an interface between the AD7862 and the

ADSP-2100. The

CONVST signal can be supplied from the

ADSP-2100 or from an external source. The AD7862 BUSY

line provides an interrupt to the ADSP-2100 when conversion is

completed on all four channels. The four conversion results can

then be read from the AD7862 using four successive reads to

the same memory address. The following instruction reads one

of the four results (this instruction is repeated four times to read

all four results in sequence):

MR0 = DM(ADC)

where MR0 is the ADSP-2100 MR0 register, and ADC is the

AD7862 address.

OPTIONAL

DMA0

DMA13

DMD15

DMD0

DMS

ADDR

DECODE

ADDRESS BUS

ADSP-2100

(ADSP-2101/

ADSP-2102)

* ADDITIONAL PINS OMITTED FOR CLARITY

DATA BUS

CONVST

DB11

DB0

BUSY

AD7862*

IRQn

DMRD (RD)

Figure 14. AD7862–ADSP-2100 Interface

AD7862–ADSP-2101/ADSP-2102 INTERFACE

The interface outlined in Figure 14 also forms the basis for an

interface between the AD7862 and the ADSP-2101/ADSP-2102.

The READ line of the ADSP-2101/ADSP-2102 is labeled

RD.

In this interface, the

RD pulse width of the processor can be

programmed using the Data Memory Wait State Control Register.

The instruction used to read one of the four results is outlined

for the ADSP-2100.

AD7862–TMS32010 Interface

An interface between the AD7862 and the TMS32010 is shown

in Figure 15. Once again, the

CONVST signal can be supplied

from the TMS32010 or from an external source, and the

TMS32010 is interrupted when both conversions have been

completed. The following instruction is used to read the conver-

sion results from the AD7862:

IN D,ADC

where D is Data Memory address, and ADC is the AD7862

address.

OPTIONAL

PA0

PA2

D15

MEN

ADDR

DECODE

ADDRESS BUS

TMS32010

* ADDITIONAL PINS OMITTED FOR CLARITY

DATA BUS

CONVST

DB11

DB0

BUSY

AD7862*

INT

DEN

Figure 15. AD7862–TMS32010 Interface

AD7862–TMS320C25 Interface

Figure 16 shows an interface between the AD7862 and the

TMS320C25. As with the two previous interfaces, conversion

can be initiated from the TMS320C25 or from an external

source, and the processor is interrupted when the conversion

sequence is completed. The TMS320C25 does not have a

separate

RD output to drive the AD7862 RD input directly.

This has to be generated from the processor STRB and R/

outputs with the addition of some logic gates. The

RD signal is

OR-gated with the MSC signal to provide the one WAIT state

required in the read cycle for correct interface timing. Conver-

sion results are read from the AD7862 using the following

instruction:

IN D,ADC

where D is Data Memory address and ADC is the AD7862

address.

A15

D15

ADDR

DECODE

ADDRESS BUS

OPTIONAL

DATA BUS

CONVST

DB11

DB0

BUSY

AD7862*

TMS320C25

*ADDITIONAL PINS OMITTED FOR CLARITY

INTn

R/W

STRB

MSC

READY

Figure 16. AD7862–TMS320C25 Interface

AD7862

–14–

REV. 0

Some applications may require that the conversion be initiated

by the microprocessor rather than an external timer. One option

is to decode the AD7862

CONVST from the address bus so

that a write operation starts a conversion. Data is read at the

end of the conversion sequence as before. Figure 18 shows an

example of initiating conversion using this method. Note that

for all interfaces, it is preferred that a read operation not be

attempted during conversion.

AD7862–MC68000 Interface

An interface between the AD7862 and the MC68000 is shown

in Figure 17. As before, conversion can be supplied from the

MC68000 or from an external source. The AD7862 BUSY line

can be used to interrupt the processor or, alternatively, software

delays can ensure that conversion has been completed before a

read to the AD7862 is attempted. Because of the nature of its

interrupts, the 68000 requires additional logic (not shown in

Figure 18) to allow it to be interrupted correctly. For further

information on 68000 interrupts, consult the 68000 user’s manual.

The MC68000

AS and R/W outputs are used to generate a

separate

RD input signal for the AD7862. CS is used to drive

the 68000 DTACK input to allow the processor to execute a

normal read operation to the AD7862. The conversion results

are read using the following 68000 instruction:

MOVE.W ADC,D0

where D0 is the 68000 D0 register, and ADC is the AD7862

address.

A15

D15

ADDR

DECODE

ADDRESS BUS

OPTIONAL

DATA BUS

CONVST

DB11

DB0

AD7862*

MC68000

*ADDITIONAL PINS OMITTED FOR CLARITY

DTACK

R/W

Figure 17. AD7862–MC68000 Interface

AD7862–80C196 Interface

Figure 18 shows an interface between the AD7862 and the

80C196 microprocessor. Here, the microprocessor initiates

conversion. This is achieved by gating the 80C196

WR signal

with a decoded address output (different to the AD7862

address). The AD7862 BUSY line is used to interrupt the

microprocessor when the conversion sequence is completed.

D15

ADDR

DECODE

ADDRESS BUS

ADDRESS/DATA BUS

CONVST

DB11

DB0

AD7862*

80C196

*ADDITIONAL PINS OMITTED FOR CLARITY

A15

Figure 18. AD7862–8086 Interface

Vector Motor Control

The current drawn by a motor can be split into two compo-

nents: one produces torque, and the other produces magnetic

flux. For optimal performance of the motor, these two compo-

nents should be controlled independently. In conventional

methods of controlling a three-phase motor, the current (or

voltage) supplied to the motor and the frequency of the drive are

the basic control variables; however, both the torque and flux

are functions of current (or voltage) and frequency. This

coupling effect can reduce the performance of the motor

because, if the torque is increased by increasing the frequency,

for example, the flux tends to decrease.

Vector control of an ac motor involves controlling phase in

addition to drive and current frequency. Controlling the phase

of the motor requires feedback information on the position of

the rotor relative to the rotating magnetic field in the motor.

Using this information, a vector controller mathematically

transforms the three phase drive currents into separate torque

and flux components. The AD7862, with its four-channel

simultaneous sampling capability, is ideally suited for use in

vector motor control applications.

A block diagram of a vector motor control application using the

AD7862 is shown in Figure 19. The position of the field is

derived by determining the current in each phase of the motor.

Only two phase currents need to be measured because the third

can be calculated if two phases are known. V

and V

of the

AD7862 are used to digitize this information.

Simultaneous sampling is critical to maintain the relative phase

information between the two channels. A current sensing

isolation amplifier, transformer or Hall effect sensor is used

between the motor and the AD7862. Rotor information is

obtained by measuring the voltage from two of the inputs to the

motor. V

and V

of the AD7862 are used to obtain this

information. Once again, the relative phase of the two channels

is important. A DSP microprocessor is used to perform the

mathematical transformations and control loop calculations on

the information fed back by the AD7862.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7862ARZ-3REEL

Mfr. #:

Buy AD7862ARZ-3REEL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC Simult Sampling Dual 250kSPS 12-Bit

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7862ARZ-3REEL

AD7862ARZ-3REEL

Products related to this Datasheet