AD7862
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TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7862 it is defined as:
THD dB
()
=20 log
V
2
2
+V
3
2
+V
4
2
+V
5
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
, V
4
and V
5
are the rms amplitudes of the second through the fifth
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and
(fa – 2 fb).
The AD7862 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Channel-to-Channel Isolation
Channel-to-Channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 100 kHz sine wave signal to each of the four inputs
individually. These, in turn, are individually referenced to the
other three channels whose inputs are grounded, and the ADC
output is measured to determine the level of crosstalk from the
other channel. The figure given is the worst case across all four
channels.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Positive Full-Scale Error
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal 4 × VREF – 3/2 LSB (AD7862-10
±10 V range) or VREF – 3/2 LSB (AD7862-3, ±2.5 V range)
after the Bipolar Offset Error has been adjusted out.
Positive Full-Scale Error (AD7862-2, 0 V to 2.5 V)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal VREF – 3/2 LSB after the unipolar
offset error has been adjusted out.
Bipolar Zero Error (AD7862-10, 610 V, AD7862-3, 62.5 V)
This is the deviation of the midscale transition (all 1s to all 0s)
from the ideal AGND – 1/2 LSB.
Unipolar Offset Error (AD7862-2, 0 V to 2.5 V)
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AGND + 1/2 LSB.
Negative Full-Scale Error (AD7862-1, 610 V; AD7862-3,
62.5 V)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal –4 × VREF + 1/2 LSB (AD7862-10
±10 V range) or –VREF + 1/2 LSB (AD7862-3, ±2.5 V range)
after Bipolar Zero Error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected V
AX/BX
input of the AD7862. It means that the
user must wait for the duration of the track/hold acquisition
time, after the end of conversion or after a channel change/step
input change to V
AX/BX
, before starting another conversion to
ensure that the part operates to specification.
AD7862
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CONVERTER DETAILS
The AD7862 is a high speed, low power, dual 12-bit A/D
converter that operates from a single +5 V supply. The part
contains two 4 µs successive approximation ADCs, two track/
hold amplifiers, an internal +2.5 V reference and a high speed
parallel interface. There are four analog inputs that are grouped
into two channels (A & B) selected by the A0 input. Each
channel has two inputs (V
A1
& V
A2
or V
B1
& V
B2
) that can be
sampled and converted simultaneously thus preserving the
relative phase information of the signals on both analog inputs.
The part accepts an analog input range of ±10 V (AD7862-10),
±2.5 V (AD7862-3) and 0 V–2.5 V (AD7862-2). Overvoltage
protection on the analog inputs for the part allows the input
voltage to go to ±17 V, ±7 V or +7 V, respectively, without
causing damage. The AD7862 has two operating modes, the
high sampling mode and the auto sleep mode where the part
automatically goes into sleep after the end of conversion. These
modes are discussed in more detail in the Timing and Control
Section.
Conversion is initiated on the AD7862 by pulsing the
CONVST
input. On the falling edge of
CONVST, both on-chip track/
holds are placed into hold simultaneously, and the conversion
sequence is started on both channels. The conversion clock for
the part is generated internally using a laser-trimmed clock
oscillator circuit. The BUSY signal indicates the end of
conversion, and at this time the conversion results for both
channels are available to be read. The first read after a conver-
sion accesses the result from V
A1
or V
B1
while the second read
accesses the result from V
A2
or V
B2
, depending on whether the
multiplexer select A0 is low or high, respectively. Data is read
from the part via a 12-bit parallel data bus with standard
CS
and
RD signals.
Conversion time for the AD7862 is 3.6 µs in the high sampling
mode (6 µs for the auto sleep mode), and the track/hold
acquisition time is 0.3 µs. To obtain optimum performance
from the part, the read operation should not occur during the
conversion or during 300 ns prior to the next conversion. This
allows the part to operate at throughput rates up to 250 kHz
and achieve data sheet specifications.
Track/Hold Section
The track/hold amplifiers on the AD7862 allow the ADCs to
accurately convert an input sine wave of full-scale amplitude to
12-bit accuracy. The input bandwidth of the track/hold is
greater than the Nyquist rate of the ADC even when the ADC
is operated at its maximum throughput rate of 250 kHz (i.e.,
the track/hold can handle input frequencies in excess of 125 kHz).
The track/hold amplifiers acquire input signals to 12-bit
accuracy in less than 400 ns. The operation of the track/holds is
essentially transparent to the user. The two track/hold amplifi-
ers sample their respective input channels simultaneously on the
falling edge of
CONVST. The aperture time for the track/holds
(i.e., the delay time between the external
CONVST signal and
the track/hold actually going into hold) is typically 15 ns and,
more importantly, is well matched across the two track/holds on
one device and also well matched from device to device. This
allows the relative phase information between different input
channels to be accurately preserved. It also allows multiple
AD7862s to sample more than two channels simultaneously. At
the end of conversion, the part returns to its tracking mode.
The acquisition time of the track/hold amplifiers begins at
this point.
Reference Section
The AD7862 contains a single reference pin, labelled VREF,
which either provides access to the part’s own +2.5 V reference
or to which an external +2.5 V reference can be connected to
provide the reference source for the part. The part is specified
with a +2.5 V reference voltage. Errors in the reference source
will result in gain errors in the AD7862’s transfer function and
will add to the specified full-scale errors on the part. On the
AD7862-10 and the AD7862-3, it will also result in an offset
error injected in the attenuator stage.
The AD7862 contains an on-chip +2.5 V reference. To use this
reference as the reference source for the AD7862, simply
connect a 0.1 µF disc ceramic capacitor from the VREF pin to
AGND. The voltage that appears at this pin is internally
buffered before being applied to the ADC. If this reference is
required for use external to the AD7862, it should be buffered
as the part has a FET switch in series with the reference output,
resulting in a source impedance for this output of 3 k nominal.
The tolerance on the internal reference is ±10 mV at 25°C with
a typical temperature coefficient of 25 ppm/°C and a maximum
error over temperature of ±25 mV.
If the application requires a reference with a tighter tolerance or
the AD7862 needs to be used with a system reference, the user
has the option of connecting an external reference to this VREF
pin. The external reference will effectively overdrive the internal
reference and provide the reference source for the ADC. The
reference input is buffered before being applied to the ADC
with the maximum input current of ±100 µA. Suitable reference
sources for the AD7862 include the AD680, AD780 and
REF43 precision +2.5 V references.
CIRCUIT DESCRIPTION
Analog Input Section
The AD7862 is offered as three part types; the AD7862-10,
which handles a ±10 V input voltage range; the AD7862-3,
which handles input voltage range ±2.5 V; and the AD7862-2,
which handles a 0 V to +2.5 V input voltage range.
AGND
AD7862-10/AD7862-3
V
AX
V
REF
TRACK/
HOLD
TO ADC
REFERENCE
CIRCUITRY
TO INTERNAL
COMPARATOR
R3
R2
R1
MUX
2k
+2.5V
REFERENCE
Figure 3. AD7862-10/-3 Analog Input Structure
Figure 3 shows the analog input section for the AD7862-10 and
AD7862-3. The analog input range of the AD7862-10 is ±10 V
into an input resistance of typically 33 k. The analog input
range of the AD7862-3 is ±2.5 V into an input resistance of
typically 12 k. This input is benign with no dynamic charging
AD7862
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currents, as the resistor stage is followed by a high input
impedance stage of the track/hold amplifier. For the AD7862-10,
R1 = 30 k, R2 = 7.5 k, and R3 = 10 k. For the AD7862-3,
R1 = R2 = 6.5 k and R3 is open circuit.
For the AD7862-10 and AD7862-3, the designed code transi-
tions occur on successive integer LSB values (i.e., 1 LSB,
2 LSBs, 3 LSBs . . .). Output coding is twos complement
binary with 1 LSB = FS/4096. The ideal input/output transfer
function for the AD7862-10 and AD7862-3 is shown in Table I.
Table I. Ideal Input/Output Code Table for the AD7862-10/-3
Analog Input
l
Digital Output Code Transition
+FSR/2 – 1 LSB
2
011 . . . 110 to 011 . . . 111
+FSR/2 – 2 LSBs 011 . . . 101 to 011 . . . 110
+FSR/2 – 3 LSBs 011 . . . 100 to 011 . . . 101
GND + 1 LSB 000 . . . 000 to 000 . . . 001
GND 111 . . . 111 to 000 . . . 000
GND – 1 LSB 111 . . . 110 to 111 . . . 111
–FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011
–FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010
–FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001
NOTES
1
FSR is full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with
REF IN = +2.5 V.
2
1 LSB = FSR/4096 = 4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with
REF IN = +2.5 V.
The analog input section for the AD7862-2 contains no biasing
resistors, and the V
AX/BX
pin drives the input to the multiplexer
and track/hold amplifier circuitry directly. The analog input
range is 0 V to +2.5 V into a high impedance stage with an
input current of less than 500 nA. This input is benign with no
dynamic charging currents. Once again, the designed code
transitions occur on successive integer LSB values. Output
coding is straight (natural) binary with 1 LSB = FS/4096 =
2.5 V/4096 = 0.61 mV. Table II shows the ideal input/output
transfer function for the AD7862-2.
Table II. Ideal Input/Output Code Table for the AD7862-2
Analog Input
1
Digital Output Code Transition
+FSR – 1 LSB
2
111 . . . 110 to 111 . . . 111
+FSR – 2 LSB 111 . . . 101 to 111 . . . 110
+FSR – 3 LSB 111 . . . 100 to 111 . . . 101
GND + 3 LSB 000 . . . 010 to 000 . . . 011
GND + 2 LSB 000 . . . 001 to 000 . . . 010
GND + 1 LSB 000 . . . 000 to 000 . . . 001
NOTES
1
FSR is full-scale range and is 2.5 V for AD7862-2 with VREF = +2.5 V.
2
1 LSB = FSR/4096 and is 0.61 mV for AD7862-2 with VREF = +2.5 V.
OFFSET AND FULL-SCALE ADJUSTMENT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications will require the
input signal to span the full analog input dynamic range. In such
applications, offset and full-scale error will have to be adjusted
to zero.
Figure 4 shows a circuit that can be used to adjust the offset and
full-scale errors on the AD7862 (V
A1
on the AD7862-10 version
is shown for example purposes only). Where adjustment is
required, offset error must be adjusted before full-scale error.
This is achieved by trimming the offset of the op amp driving
the analog input of the AD7862 while the input voltage is a
1/2 LSB below analog ground. The trim procedure is as follows:
apply a voltage of –2.44 mV (–1/2 LSB) at V
A1
(see Figure 4)
and adjust the op amp offset voltage until the ADC output code
flickers between 1111 1111 1111 and 0000 0000 0000.
V
1
R1
10k
R2
500
R3
10k
AGND
AD7862*
*ADDITIONAL PINS OMITTED FOR CLARITY
INPUT
RANGE = ±10V
10k
R5
10k
R4
V
A1
Figure 4. Full-Scale Adjust Circuit
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC
positive full scale). The trim procedures for both cases are as
follows:
Positive Full-Scale Adjust
Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V
A1
. Adjust
R2 until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of –9.9976 V (–FS + 1/2 LSB) at V
A1
and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
that use an external reference is to adjust the voltage at the
VREF pin until the full-scale error for any of the channels is
adjusted out. The good full-scale matching of the channels will
ensure small full-scale errors on the other channels.
TIMING AND CONTROL
Figure 5a shows the timing and control sequence required to
obtain optimum performance (Mode 1) from the AD7862. In
the sequence shown, a conversion is initiated on the falling edge
of
CONVST. This places both track/holds into hold simulta-
neously, and new data from this conversion is available in the
output register of the AD7862 3.6 µs later. The BUSY signal
indicates the end of conversion, and at this time the conversion
results for both inputs are available to be read. A second
conversion is then initiated. If the multiplexer select A0 is low,
the first and second read pulses after the first conversion accesses
the result from channel A (V
A1
and V
A2
respectively). The third

AD7862ARZ-3REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Simult Sampling Dual 250kSPS 12-Bit
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