3.3V 4K/8K/16K x 16/18 Dual-Port Static RA
CY7C024AV/025AV/026A
CY7C0241AV/0251AV/036A
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06052 Rev. *B Revised September 1, 2003
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)
• 4/8K × 18 organization (CY7C0241AV/0251AV)
• 16K × 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 and 25 ns
• Low operating power
— Active: I
CC
= 115 mA (typical)
—Standby: I
SB3
= 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
•INT
flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT70V24, 70V25, and 7V0261.
Notes:
1. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
2. I/O
0
–I/O
7
for x16 devices; I/O
0
–I/O
8
for x18 devices.
3. A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices.
4. BUSY
is an output in master mode and an input in slave mode.
R/W
L
OE
L
I/O
8/9L
–I/O
15/17L
I/O
Control
Address
Decode
A
0L
–A
11/12/13L
CE
L
OE
L
R/W
L
BUSY
L
I/O
Control
CE
L
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
UB
L
LB
L
I/O
0L
–I/O
7/8L
R/W
R
OE
R
I/O
8/9L
–I/O
15/17R
CE
R
UB
R
LB
R
I/O
0L
–I/O
7/8R
UB
L
LB
L
A
0L
–A
11/1213L
True Dual-Ported
RAM Array
A
0R
–A
11/12/13R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
UB
R
LB
R
Address
Decode
A
0R
–A
11/12/13R
[1]
[1]
[2]
[2]
[4]
[4]
12/13/14
8/9
8/9
12/13/14
8/9
8/9
12/13/14 12/13/14
[3]
[3]
[3]
[3]
