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CY7C025AV-20AC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY7C024AV/025AV/026A
V
CY7C0241AV/0251AV/036A
V
Document #: 38-06052 Rev. *B Page 13 of 19
Notes:
41. CE
= HIGH for the duration of the above timing (both write and read cycle).
42. I/O
0R
= I/O
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH.
43. Semaphores are reset (available to both ports) at cycle start.
44. If t
SPS
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Switching Waveforms (continued)
t
SOP
t
SAA
VALID ADRESS VALID ADRESS
t
HD
DATA
IN
VALID
DATA
OUT
VALID
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O
0
SEM
A
0
–A
2
Semaphore Read After Write Timing, Either Side
[41]
MATCH
t
SPS
A
0L
–A
2L
MATCH
R/W
L
SEM
L
A
0R
–A
2R
R/W
R
SEM
R
T
iming Diagram of Semaphore Contention
[42, 43, 44]
CY7C024AV/025AV/026A
V
CY7C0241AV/0251AV/036A
V
Document #: 38-06052 Rev. *B Page 14 of 19
Note:
45. CE
L
= CE
R
= LOW.
Switching Waveforms (continued)
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA IN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
Timing Diagram of Read with BUSY (M/S=HIGH)
[45]
t
PWE
R/W
BUSY
t
WB
t
WH
W
rite Timing with Busy Input (M/S=LOW)
CY7C024AV/025AV/026A
V
CY7C0241AV/0251AV/036A
V
Document #: 38-06052 Rev. *B Page 15 of 19
Note:
46. If t
PS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Switching Waveforms (continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CE
R
ValidFirst:
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
B
usy Timing Diagram No.1 (CE Arbitration)
[46]
C
E
L
Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right AddressValid First:
Busy Timing Diagram No.2 (Address Arbitration)
[46]
L
eft Address Valid First:
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY7C025AV-20AC

Mfr. #:
Buy CY7C025AV-20AC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 128K PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
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