Read/Write Time Slots
Data communication with the DS28E83 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 4 illustrates the
definitions of the write and read time slots.
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
the threshold V
TL
, the DS28E83 starts its internal timing
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line must
have crossed the V
TH
threshold before the write-one low
time t
W1LMAX
is expired. For a write-zero time slot, the
voltage on the data line must stay below the V
TH
thresh-
old until the write-zero low time t
W0LMIN
is expired. For
the most reliable communication, the voltage on the data
line should not exceed V
ILMAX
during the entire t
W0L
or
t
W1L
window. After the V
TH
threshold has been crossed,
the DS28E83 needs a recovery time t
REC
before it is
ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot. The
voltage on the data line must remain below V
TL
until the
read low time t
RL
is expired. During the t
RL
window, when
responding with a 0, the DS28E83 starts pulling the data
line low; its internal timing generator determines when this
pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28E83 does not hold the data
line low at all, and the voltage starts rising as soon as t
RL
is over.
The sum of t
RL
+ δ (rise time) on one side and the internal
timing generator of the DS28E83 on the other side define
the master sampling window (t
MSRMIN
to t
MSRMAX
), in
which the master must perform a read from the data line.
For the most reliable communication, t
RL
should be as
short as permissible, and the master should read close
to but no later than t
MSRMAX
. After reading from the data
line, the master must wait until t
SLOT
is expired. This
guarantees sufficient recovery time t
REC
for the DS28E83
to get ready for the next time slot. Note that t
REC
speci-
fied herein applies only to a single DS28E83 attached to a
1-Wire line. For multidevice configurations, t
REC
must be
extended to accommodate the additional 1-Wire device
input capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as the
special 1-Wire line drivers can be used.
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10
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
Figure 4. Read/Write Timing Diagrams
t
W1L
t
SLOT
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
RESISTOR (R
PUP
)
MASTER
t
F
RESISTOR (R
PUP
)
MASTER 1-WIRE SLAVE
WRITE-ONE TIME SLOT
t
W0L
t
SLOT
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
RESISTOR (R
PUP
)
MASTER
t
F
WRITE-ZERO TIME SLOT
t
REC
t
SLOT
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
δ
t
F
READ-DATA TIME SLOT
t
REC
t
RL
t
MSR
MASTER SAMPLING
WINDOW
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11
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
1-Wire ROM Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that
the DS28E83 supports. All ROM function commands are
8 bits long. For operational details, see the flowchart
description in Figure 5 and Figure 6. A descriptive list of
these ROM function commands follows in the subsequent
sections.
Read ROM[33h]
The Read ROM command allows the bus master to read
the DS28E83’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM[55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28E83 on a multidrop bus. Only the DS28E83 that
exactly matches the 64-bit ROM sequence responds
to the subsequent device function command. All other
slaves wait for a reset pulse. This command can be used
with a single device or multiple devices on the bus.
Search ROM[F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit in the ID number, starting with the least sig-
nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
Skip ROM [CCh]
This command can save time in a single-drop bus system
by allowing the bus master to access the device functions
without providing the 64-bit ROM ID. If more than one
slave is present on the bus and, for example, a read com-
mand is issued following the Skip ROM command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
Resume [A5h]
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the device function commands, similar
to a Skip ROM command. The only way to set the RC bit
is through successfully executing the Match ROM, Search
ROM, or Overdrive-Match ROM command. Once the RC
bit is set, the device can repeatedly be accessed through
the Resume command. Accessing another device on the
bus clears the RC bit, preventing two or more devices from
simultaneously responding to the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the device functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM command
sets the DS28E83 into the overdrive mode (OD = 1). All
communication following this command must occur at
overdrive speed until a reset pulse of minimum 480μs
duration resets all devices on the bus to standard speed
(OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-bit
ROM sequence transmitted at overdrive speed allows the
bus master to address a specific DS28E83 on a multi-
drop bus and to simultaneously set it in overdrive mode.
Only the DS28E83 that exactly matches the 64-bit ROM
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DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator

DS28E83Q+U

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Security ICs / Authentication ICs 1-WIRE 5K RAD SECURE AUTHENTICATOR
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