sequence responds to the subsequent device function
command. Slaves already in overdrive mode from a previ-
ous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrive-
capable slaves return to standard speed at the next reset
pulse of minimum 480μs duration. The Overdrive-Match
ROM command can be used with a single device or mul-
tiple devices on the bus.
ROM Command Flow
Figure 5. ROM Function Flow (Part 1)
BUS MASTER Tx
ROM FUNCTION COMMAND
OD
RESET PULSE?
BUS MASTER Tx
RESET PULSE
F0h
SEARCH ROM
COMMAND?
SLAVE Tx
SERIAL NUMBER
(6 BYTES)
SLAVE Tx
FAMILY CODE
(1 BYTE)
Y
N
Y
N
Y
OD = 0
SLAVE Tx
PRESENCE PULSE
33h
READ ROM
COMMAND?
55h
MATCH ROM
COMMAND?
N
CCh
SKIP ROM
COMMAND?
N N
RC = 0 RC = 0
RC = 0
RC = 0
MASTER Tx BIT 0
SLAVE Tx BIT 0
SLAVE Tx BIT 0
MASTER Tx BIT 0
SLAVE Tx BIT 1
SLAVE Tx BIT 1
MASTER Tx BIT 0
MASTER Tx BIT 1
Y Y Y Y
Y
SLAVE Tx BIT 63
SLAVE Tx BIT 63
MASTER Tx BIT 63
RC = 1
BIT 63 MATCH?
BIT 1 MATCH?
BIT 0 MATCH?
BIT 0 MATCH?
FROM DEVICE FUNCTIONS
FLOW CHART
BIT 1 MATCH?
MASTER Tx BIT 63
RC = 1
BIT 63 MATCH?
Y Y
N
N
N
N
N
N
SLAVE Tx
CRC BYTE
TO ROM FUNCTION
FLOW PART 2
TO ROM FUNCTION
FLOW PART 2
FROM ROM FUNCTION FLOW PART 2
FROM ROM FUNCTION FLOW PART 2
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Maxim Integrated
13
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
Figure 6. ROM Function (Part 2)
69h
OVERDRIVE-
MATCH ROM?
TO DEVICE FUNCTIONS
FLOW CHART
N
Y
A5h
RESUME
COMMAND?
3Ch
OVERDRIVE-
SKIP ROM?
N
N
RC = 0; OD = 1
MASTER Tx BIT 0
MASTER Tx BIT 1
Y Y Y
N
SLAVE Tx BIT 63
RC = 1
BIT 63 MATCH?
BIT 1 MATCH?
BIT 0 MATCH?
MASTER Tx
RESET?
RC = 1?
MASTER Tx
RESET?
Y
N
Y
N
RC = 0; OD = 1
OD = 0
N
OD = 0
N
OD = 0
N
Y
TO ROM FUNCTION FLOW PART 1
FROM ROM
FUNCTION
FLOW PART 1
FROM ROM FUNCTION
FLOW PART 1
TO ROM FUNCTION FLOW PART 1
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Maxim Integrated
14
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator
Improved Network Behavior (Switch-Point
Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization with
the master and, consequently, result in a Search ROM
command coming to a dead end or cause a device-spe-
cific function command to abort. For better performance
in network applications, the DS28E83 uses a 1-Wire front-
end that is less sensitive to noise.
The DS28E83’s 1-Wire front end has the following features:
The falling edge of the presence pulse has a con-
trolled slew rate to reduce ringing. The slew rate con-
trol is specified by t
FPD
.
There is a hysteresis at the low-to-high switching
threshold V
TH
. If a negative glitch crosses V
TH
, but
does not go below V
TH
- V
HY
, it is not recognized
(Figure 7, Case A). The hysteresis is effective at any
1-Wire speed.
There is a time window specified by the rising edge
hold-off time t
REH
during which glitches are ignored,
even if they extend below the V
TH
- V
HY
threshold
(Figure 7, Case B, t
GL
< t
REH
). Deep voltage drops
or glitches that appear late after crossing the V
TH
threshold and extend beyond the t
REH
window can-
not be filtered out and are taken as the beginning of
a new time slot (Figure 7, Case C, t
GL
t
REH
).
Figure 7. Noise Suppression Scheme
V
PUP
V
TH
V
HY
t
REH
t
GL
t
REH
t
GL
0V
CASE A CASE B CASE C
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Maxim Integrated
15
DS28E83 DeepCover Radiation Resistant
1-Wire Authenticator

DS28E83Q+U

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Security ICs / Authentication ICs 1-WIRE 5K RAD SECURE AUTHENTICATOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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